Chapter 8: Main Memory: Silberschatz, Galvin and Gagne ©2013 Operating System Concepts - 9 Edition
Chapter 8: Main Memory: Silberschatz, Galvin and Gagne ©2013 Operating System Concepts - 9 Edition
Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013
Chapter 8: Memory Management
Background
Swapping
Contiguous Memory Allocation
Segmentation
Paging
Structure of the Page Table
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Objectives
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Background
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Base and Limit Registers
A pair of base and limit registers define the logical address space
CPU must check every memory access generated in user mode to
be sure it is between base and limit for that user
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Hardware Address Protection
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Address Binding
Programs on disk, ready to be brought into memory to execute form an
ready queue
Further, addresses represented in different ways at different stages of a
program’s life
Source code addresses usually symbolic
Compiled code addresses bind to relocatable addresses
i.e. “14 bytes from beginning of this module”
Linker or loader will bind relocatable addresses to absolute addresses
i.e. 74014
Each binding maps one address space to another
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Binding of Instructions and Data to Memory
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Logical vs. Physical Address Space
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Memory-Management Unit (MMU)
Hardware device that at run time maps virtual to physical
address
Many methods possible, covered in the rest of this chapter
To start, consider simple scheme where the value in the
relocation register is added to every address generated by a
user process at the time it is sent to memory
Base register now called relocation register
The user program deals with logical addresses; it never sees the
real physical addresses
Execution-time binding occurs when reference is made to
location in memory
Logical address bound to physical addresses
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Dynamic relocation using a relocation register
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Dynamic Linking
Static linking – system libraries and program code combined by
the loader into the binary program image
Dynamic linking –linking postponed until execution time
Operating system checks if routine is in processes’ memory
address
If not in address space, add to address space
Dynamic linking is particularly useful for libraries
System also known as shared libraries
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Swapping
A process can be swapped temporarily out of memory to a
backing store, and then brought back into memory for continued
execution
Total physical memory space of processes can exceed
physical memory
Backing store – disk large enough to accommodate copies of
all memory images for all users; must provide direct access to
these memory images
Roll out, roll in – swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and executed
Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped
System maintains a ready queue of ready-to-run processes
which have memory images on disk
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Swapping (Cont.)
Does the swapped out process need to swap back in to same
physical addresses?
Depends on address binding method
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Schematic View of Swapping
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Context Switch Time including Swapping
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Context Switch Time and Swapping (Cont.)
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Contiguous Allocation
Main memory must support both OS and user processes
Limited resource, must allocate efficiently
Contiguous allocation is one early method
Main memory usually into two partitions:
Resident operating system, usually held in low memory with
interrupt vector
User processes then held in high memory
Each process contained in single contiguous section of
memory
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Contiguous Allocation (Cont.)
Relocation registers used to protect user processes from each
other, and from changing operating-system code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each
logical address must be less than the limit register
MMU maps logical address dynamically
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Hardware Support for Relocation and Limit Registers
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Multiple-partition allocation
Multiple-partition allocation
Degree of multiprogramming limited by number of partitions
Variable-partition sizes for efficiency (sized to a given process’ needs)
Hole – block of available memory; holes of various size are scattered
throughout memory
When a process arrives, it is allocated memory from a hole large enough to
accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
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Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
First-fit and best-fit better than worst-fit in terms of speed and storage
utilization
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Fragmentation
External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
Internal Fragmentation – allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used
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Fragmentation (Cont.)
Reduce external fragmentation by compaction
Shuffle memory contents to place all free memory together
in one large block
Compaction is possible only if relocation is dynamic, and is
done at execution time
Now consider that backing store has same fragmentation
problems
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Segmentation
Memory-management scheme that supports user view of memory
A program is a collection of segments
A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
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User’s View of a Program
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Logical View of Segmentation
4
1
3 2
4
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Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>,
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Segmentation Architecture (Cont.)
Protection
With each entry in segment table associate:
validation bit = 0 illegal segment
read/write/execute privileges
Protection bits associated with segments; code sharing
occurs at segment level
Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
A segmentation example is shown in the following diagram
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Segmentation Hardware
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Paging
Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
Avoids external fragmentation
Avoids problem of varying sized memory chunks
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and
load program
Set up a page table to translate logical to physical addresses
Backing store likewise split into pages
Still have Internal fragmentation
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Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit
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Paging Hardware
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Paging Model of Logical and Physical Memory
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Paging Example
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Paging (Cont.)
Calculating internal fragmentation
Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
Worst case fragmentation = 1 frame – 1 byte
On average fragmentation = 1 / 2 frame size
So small frame sizes desirable?
But each page table entry takes memory to track
Page sizes growing over time
Solaris supports two page sizes – 8 KB and 4 MB
Process view and physical memory now very different
By implementation process can only access its own memory
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Free Frames
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Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page
table
In this scheme every data/instruction access requires two
memory accesses
One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)
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Implementation of Page Table (Cont.)
Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access
next time
Replacement policies must be considered
Some entries can be wired down for permanent fast
access
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Associative Memory
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Paging Hardware With TLB
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Effective Access Time
Associative Lookup = time unit
Can be < 10% of memory access time
Hit ratio =
Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative
registers
Consider = 80%, = 20ns for TLB search, 100ns for memory access
Effective Access Time (EAT)
EAT = (1 + ) + (2 + )(1 – )
=2+–
Consider = 80%, = 20ns for TLB search, 100ns for memory access
EAT = 0.80 x 100 + 0.20 x 200 = 120ns
Consider more realistic hit ratio -> = 99%, = 20ns for TLB search,
100ns for memory access
EAT = 0.99 x 100 + 0.01 x 200 = 101ns
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Memory Protection
Memory protection implemented by associating protection bit
with each frame to indicate if read-only or read-write access is
allowed
Can also add more bits to indicate page execute-only, and
so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the process’
logical address space, and is thus a legal page
“invalid” indicates that the page is not in the process’ logical
address space
Or use page-table length register (PTLR)
Any violations result in a trap to the kernel
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Valid (v) or Invalid (i) Bit In A Page Table
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Shared Pages
Shared code
One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems)
Similar to multiple threads sharing the same process space
Also useful for interprocess communication if sharing of
read-write pages is allowed
Private code and data
Each process keeps a separate copy of the code and data
The pages for the private code and data can appear
anywhere in the logical address space
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Shared Pages Example
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Structure of the Page Table
Memory structures for paging can get huge using straight-forward
methods
Consider a 32-bit logical address space as on modern
computers
Page size of 4 KB (212)
Page table would have 1 million entries (2 32 / 212)
If each entry is 4 bytes -> 4 MB of physical address space /
memory for page table alone
That amount of memory used to cost a lot
Don’t want to allocate that contiguously in main memory
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables
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Hierarchical Page Tables
Break up the logical address space into multiple page
tables
A simple technique is a two-level page table
We then page the page table
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Two-Level Page-Table Scheme
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Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
Thus, a logical address is as follows:
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Address-Translation Scheme
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64-bit Logical Address Space
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Three-level Paging Scheme
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Hashed Page Tables
Common in address spaces > 32 bits
The virtual page number is hashed into a page table
This page table contains a chain of elements hashing to the same
location
Each element contains (1) the virtual page number (2) the value of the
mapped page frame (3) a pointer to the next element
Virtual page numbers are compared in this chain searching for a match
If a match is found, the corresponding physical frame is extracted
Variation for 64-bit addresses is clustered page tables
Similar to hashed but each entry refers to several pages (such as
16) rather than 1
Especially useful for sparse address spaces (where memory
references are non-contiguous and scattered)
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Hashed Page Table
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Inverted Page Table
Rather than each process having a page table and keeping track
of all possible logical pages, track all physical pages
One entry for each real page of memory
Entry consists of the virtual address of the page stored in that real
memory location, with information about the process that owns that
page
Decreases memory needed to store each page table, but
increases time needed to search the table when a page reference
occurs
Use hash table to limit the search to one — or at most a few —
page-table entries
TLB can accelerate access
But how to implement shared memory?
One mapping of a virtual address to the shared physical
address
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Inverted Page Table Architecture
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Oracle SPARC Solaris
Consider modern, 64-bit operating system example with tightly
integrated HW
Goals are efficiency, low overhead
Based on hashing, but more complex
Two hash tables
One kernel and one for all user processes
Each maps memory addresses from virtual to physical memory
Each entry represents a contiguous area of mapped virtual
memory,
More efficient than having a separate hash-table entry for
each page
Each entry has base address and span (indicating the number
of pages the entry represents)
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End of Chapter 8
Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013