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CHAPTER 7 :
LATCHES, FLIP-FLOPS AND
TIMER
 Chapter 7 :
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FLIP-FLOPS AND RELATED DEVICE
 7.1 Latches
 7.2 Edge-Triggered Flip-Flops
 7.3 Master-Slave Flip Flops
 7.4 Flip-Flop Operating Characteristics
 7.5 Flip-Flop Application
 7.6 One Shot (ringkas)
 7.7 The 555 Timer (ringkas)
 7.1 Latches
3  A latch is a type of temporary storage device that has
two stable states (bistable) a is normally placed in a
category separate from that of flip-flops.
 Latch are basically similar to flip-flop.
 The difference between latch and flip-flop is in the
method used for changing their state.
 S – set; R-reset
 Type of Latch :
 A) S-R Latch
 B) Gated S-R Latch
 C) Gated D Latch
A) S-R (Set-Reset) Latch
 The output of each gate is connected to an input of the
opposite data.
 This produces a regenerative feedback.

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 Logic Symbol : S-R and S-R
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Latch
 Truth-Tables :
For Active-HIGH and Active-LOW input SR-Latch
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Active-HIGH Active-LOW

INPUTS OUTPUTS INPUTS OUTPUTS

COMMENTS COMMENTS
S R Q Q S R Q Q
No change. Latch remains in
0 0 NC NC present state
0 0 1 1 Invalid condition

0 1 0 1 Latch RESET 0 1 1 0 Latch SET

1 0 1 0 Latch SET 1 0 0 1 Latch RESET

No change. Latch remains in

1 1 0 0 Invalid condition 1 1 NC NC present state

 The Q and not-Q outputs are supposed to be in opposite states.

 Q=1 and not-Q=0 is defined as set (by making S=1 and R=0)
 Q=0 and not-Q=1 is conversely defined as reset (by making S=0 and R=1)
 When S and R are both equal to 0, the multivibrator's outputs “not change" in

their prior states.

 If Q and not-Q happen to be forced to the same state (both 0 or both 1), that
state is referred to as invalid.
 Example : S-R Latch
7 If the S and R waveforms in Figure 7.1(a) are applied to the inputs of
the latch in Figure 7.1(b), determine the waveform that will be observed
on the Q output. Assume that Q is initially LOW

(a) R

(b) Q
Figure 7.1
 Example : S-R Latch

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 Review : S-R Latch
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 A bistable multivibrator is one with two stable
output states.
 In an S-R latch, activation of the S input sets the
circuit, while activation of the R input resets the
circuit. If both S and R inputs are activated
simultaneously, the circuit will be in an invalid
condition.
 A race condition is a state in a sequential system
where two mutually-exclusive events are
simultaneously initiated by a single cause.
B) Gated S-R Latch
 Is a gated latch requires an enable input (EN).
 The S and R inputs control the state to which the latch will
go when a HIGH level is applied to the EN input.
 The latch will not change until EN is HIGH, but as long as
it remains HIGH, the output is controlled by the state of
the S and R input.
 The invalid state occurs when both S and R are
simultaneously HIGH.

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 B) Gated S-R Latch
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B) Gated S-R Latch (Truth
Table)
EN S R Output
0 0 0 No Change
0 0 1 No Change
0 1 0 No Change
0 1 1 No Change
1 0 0 No Change
1 0 1 Q=0
1 1 0 Q=1
1 1 1 Invalid

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 Example 1 : Gated S-R Latch
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 Example 2 : Gated S-R Latch.
Find waveform for Q.
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EN
 Example 2 : Gated S-R Latch. ANSWER
S

EN

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 C) Gated D Latch
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B) Gated D Latch (Truth Table)
EN D Output
0 0 No Change
0 1 No Change
1 0 Q=0
1 1 Q=1

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 Example : Gated D Latch
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 7.2 Edge-Triggered Flip-Flops

Flip-flops are synchronous bi-stable storage devices

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

capable of storing one bit.

 In this case synchronous means that the output state
only changes at a specified point on a triggering input
called the clock (C).
 That is, the output changes are synchronized with the
clock signal.
 7.2 Edge-Triggered Flip-Flops
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 The main difference between latches and flip-flops is the
method used to change their states.
 Latches are level sensitive, or level-triggered. This
means that the outputs are dependent on the voltage level
applied, not on any signal transition.
 Flip-flops are edge-triggered, that is that they depend on
the transition of a signal.
 This may either be a LOW-to-HIGH (rising edge) or a
HIGH-to-LOW (falling edge) transition.
 Difference between latch and flip-flop
Set
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Reset

Latch

Set

Reset

Clock
Jam

Flip-Flop
 7.2 Edge-Triggered Flip-Flops

Three types of Edge-Triggered FF:

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

 i) Edge-Triggered S-R Flip Flop

 ii) Edge-Triggered D Flip Flop
 iii) Edge-Triggered J-K Flip Flop
7.2 Edge-Triggered Flip-Flops

Figure : Edge-Triggered FF logic symbol

(top: positive edge-triggered; bottom: negative edge-triggered)

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i) Edge-Triggered S-R Flip-Flops

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 i) Edge-Triggered S-R Flip Flop
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S R CLK Output Comments TRUTH TABLE

Q Q
0 0 X Q0 Q0 No Change = clock transition
LOW
0 1 0 1 RESET to HIGH
X = irrelevent
1 0 1 0 SET (don’t care)
Q0= output level prior to
1 1 ? ? Invalid
clock transition

Example
Example : Edge.. S-R Flip-Flops

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 ii) Edge-Triggered D Flip Flop
27  D FF is useful when a single data bit (1 or 0) is to be

stored.
 The addition of an inverter to an S-R FF creates
basic D FF where a positive edge-triggered type is

shown.
ii) Edge-Triggered D Flip Flop
TRUTH TABLE (for positive edge-
triggered)
INPUTS OUTPUTS COMMENTS
D CLK Q Q’
1 1 0 SET (store a 1)
0 0 1 RESET (store 0)

Remember, Q follows D at the active or triggering clock edge.

Example : Determine Q for the D input

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 iii) Edge-Triggered J-K Flip Flop
The JK FF is versatile and is a widely used
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

type of FF.
 The difference between J-K and S-R is a J-K
has no invalid state as SR.

Logic Symbol
 iii) Edge-Triggered J-K Flip Flop
30 J K CLK Output Comments TRUTH TABLE
Q Q
0 0 Q0 Q0 No Change = clock transition
LOW
0 1 0 1 RESET
to HIGH
1 0 1 0 SET Q0= output level prior to
1 1 Q0 Q0 Toggle clock transition

Positive or
negative
triggered ?
 Example : Edge.. J-K Flip-Flops
31 Top :
positive
edge-
triggered
Bottom:
negative
edge-
triggered
 iii) Edge-Triggered J-K Flip Flop
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 Asynchronous :
Presets (PRE) and Clear (CLR) inputs
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 Synchronous  inputs transferred on the triggering

edge of the clock
 Asynchronous  inputs effect FF state
independent of the clock
 Normally labeled
 preset (PRE) & clear (CLR) OR
 direct set (SD) & direct reset (RD)
34

PRE CLR FF MODE

0 SET Asynchronous

0 RESET Asynchronous

1 1 JK Synchronous
 Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.

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 Q

clk
pulse
PRE CLR J K FF Comment

1,2,3 0 1 1 SET JK inputs - dont care

4,5,6,
1 1 1 1 Toggle Synchronous mode.
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8,9 0 1 1 RESET JK inputs - dont care

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 Example 1 : PRE and CLR
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 Example 2 : PRE and CLR
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 7.3 Master-Slave Flip Flops
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2 sections :

Master section - a) External JK input, b) A gated latch

Slave section - a) Inputs = outputs of Master, b) Inverted clock pulse
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41
Multivibrator
quasi stable
 Monostable (1 stable state)
stable
 Ex : One-Shot
 Analogi ‘start motor’,
alarm clock

 Bi-stable (2 stable state)

Ex : Latch, Flip-Flop

 Astable (no stable state)

Ex : Clock

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END OF CHAPTER 7