MPMC Unit4
MPMC Unit4
MPMC Unit4
8051 Family
The 8051 is a subset of the 8052
The 8031 is a ROM-less 8051
Add external ROM to it
You lose two ports, and leave only 2 ports for I/O
operations
2
Introduction to
8051
MICROCONTROLLER
3
8051 Microcontroller
Intel introduced 8051, developed in the year
1981.
The 8051 is an 8-bit controller.
D0-D7 DATA LINES
A0-A15 ADDRESS LINES
UNIT 4 Syllabus
• Architecture of 8051
• Special Function Registers(SFRs)
• I/O Pins Ports and Circuits {Pin Diagram}
• Instruction set
• Addressing modes
• Assembly language programming
4
General Block Diagram of 8051 5
External Interrupts
8bit
CPU
Bus Serial
OSC 4 I/O Ports
Control Port
TXD RXD
P0 P1 P2 P3
8051 Features 6
8 bit CPU
On-chip clock oscillator
4K bytes of on-chip Program Memory-ROM
128 bytes of on-chip Data RAM
64KB Program Memory address space
64KB Data Memory address space
32 bidirectional I/0 lines (Port 0,1,2,3)
Port 0 { P0.0-P0.7 } – 8 pins
Port 1 { P1.0-P1.7 } – 8 pins
Port 2 { P2.0-P2.7 } – 8 pins
Port 3 { P3.0-P3.7 } – 8 pins
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Two 16-bit timer/counters(Timer 1,Timer 0)
One serial port
UART(Universal Asynchronous Receiver Transmitter)
6-source interrupt structure
1. External interrupt INT0
2. Timer interrupt T0
3. External interrupt INT1
4. Timer interrupt T1
5. Serial communication interrupt
6. Timer Interrupt T2
4 Register Banks (Bank 0, Bank 1, Bank 2, Bank 3)
each bank has R0-R7 registers
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Pin Description
of the 8051
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10
I/O Port Pins
The four 8-bit I/O ports
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Port 3
Port 3 can be used as input or output.
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Pin Description Summary
PIN TYPE NAME AND FUNCTION
P0.0 - P0.7 I/O Port 0: Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data
memory.
P1.0 - P1.7 I/O Port 1: Port 1 is an 8-bit bi-directional simple I/O port.
P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.
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Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: resets the device.
ALE O Address Latch Enable:
When ALE=0, it provides data D0-D7
When ALE=1, it has address A0-A7
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Architecture of
8051
microcontroller
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16
17
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Bank 3 R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 R0 R1 R2 R3 R4 R5 R6 R7
Bank 0 R0 R1 R2 R3 R4 R5 R6 R7
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Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1
00-Bank 0
01-Bank 1
10-Bank 2
11-Bank 3
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Data Pointer Register (DPTR)
It consists of two separate registers:
DPH (Data Pointer High) &
DPL (Data Pointer Low).
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Stack Pointer (SP) Register
8 bit
8 bit
8 bit
8 bit
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INSTRUCTION
SET OF
8051
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8051 Instruction Set
The instructions are grouped into 5 groups
Arithmetic
Logic
Data Transfer
Boolean
Branching
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1. Arithmetic Instructions
ADD A, source
A A + <operand>.
ADDC A, source
A A + <operand> + CY.
SUBB A, source
A A - <operand> - CY{borrow}.
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INC
Increment the operand by one. Ex: INC DPTR
DEC
Decrement the operand by one. Ex: DEC B
MUL AB
A*B
Multiplication Result
8 byte * 8 byte A=low byte,
B=high byte
DIV AB
A/B
Division Quotient Remainder
8 byte /8 byte
A B
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Multiplication of Numbers
MUL AB ; A B, place 16-bit result in B
and A
A=07 , B=02
MUL AB ;07 * 02 = 000E where B = 00 and A = 0E
Division of Numbers
DIV AB ; A / B , 8-bit Quotient result in A &
8-bit Remainder result in B
A=07 , B=02
DIV AB ;07 / 02 = Quotient 03(A) Remainder 01 (B)
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2. Logical
instructions
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ANL D,S
-Performs logical AND of destination & source
- Eg: ANL A,#0FH ANL A,R5
ORL D,S
-Performs logical OR of destination & source
- Eg: ORL A,#28H ORL A,@R0
XRL D,S
-Performs logical XOR of destination & source
- Eg: XRL A,#28H XRL A,@R0
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CPL A
-Compliment accumulator
-gives 1’s compliment of accumulator data
RL A
-Rotate data of accumulator towards left without carry
RLC A
- Rotate data of accumulator towards left with carry
RR A
-Rotate data of accumulator towards right without carry
RRC A
- Rotate data of accumulator towards right with carry
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3. Data Transfer
Instructions
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MOV Instruction
MOV destination, source ; copy source to destination.
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MOVX
Data transfer between the accumulator and
a byte from external data memory.
MOVX A, @DPTR
MOVX @DPTR, A
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PUSH / POP
Push and Pop a data byte onto the stack.
PUSH DPL
POP 40H
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XCH
Exchange accumulator and a byte variable
XCH A, Rn
XCH A, direct
XCH A, @Ri
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4.Boolean variable
instructions
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CLR:
The operation clears the specified bit indicated in
the instruction
Ex: CLR C clear the carry
SETB:
The operation sets the specified bit to 1.
CPL:
The operation complements the specified bit
indicated in the instruction
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ANL C,<Source-bit>
ORL C,<Source-bit>
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XORL C,<Source-bit>
MOV P2.3,C
MOV C,P3.3
MOV P2.0,C
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5. Branching
instructions
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Jump Instructions
LJMP (long jump):
Original 8051 has only 4KB on-chip ROM
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Call Instructions
LCALL (long call):
Target address within 64K-byte range
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2 forms for the return instruction:
Return from subroutine – RET
Return from ISR – RETI
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8051
Addressing
Modes
8051 Addressing Modes
The CPU can access data in various ways, which are
called addressing modes
1. Immediate
2. Register
3. Direct
4. Indirect
5. Relative
6. Absolute
7. Long
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1. Immediate Addressing Mode
The immediate data sign, “#”
Data is provided as a part of instruction.
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2. Register Addressing Mode
In the Register Addressing mode, the instruction involves
transfer of information between registers.
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3. Direct Addressing Mode
This mode allows you to specify the operand by giving its
actual memory address
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4. Indirect Addressing Mode
A register is used as a pointer to the data.
Only register R0 and R1 are used for this purpose.
R2 – R7 cannot be used to hold the address of an
operand located in RAM.
When R0 and R1 hold the addresses of RAM locations,
they must be preceded by the “@” sign.
MOVX A,@DPTR
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5. Relative Addressing
This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional
jumps like JNZ
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6. Absolute Addressing
In Absolute Addressing mode, the absolute
address, to which the control is transferred, is
specified by a label.
Two instructions associated with this mode
of addressing are ACALL and AJMP
instructions.
These are 2-byte instructions
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7. Long Addressing
This mode of addressing is used with the
LCALL and LJMP instructions.
It is a 3-byte instruction
It allows use of the full 64K code space.
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8051
Assembly
Language
Programming(ALP)
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ADDITION OF TWO 8 bit Numbers
ADDRESS LABEL MNEMONICS
9100: CLR C
MOV A,#05
MOV B,#03
SUBB A,B
MOV DPTR,#9200
MOVX @DPTR,A
HERE SJMP HERE
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After execution: A=02
MULTIPLICATION OF TWO DIVISION OF TWO 8 bit
8 bit Numbers Numbers
Address Label Mnemonics Address Label Mnemonics
MUL AB DIV AB