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Ch8 - Main Memory
Ch8 - Main Memory
Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013
Background
Operating System Concepts – 9th Edition 8.2 Silberschatz, Galvin and Gagne ©2013
Base and Limit Registers
A pair of base and limit registers define the logical address space
CPU must check every memory access generated in user mode to
be sure it is between base and limit for that user
Operating System Concepts – 9th Edition 8.3 Silberschatz, Galvin and Gagne ©2013
Hardware Address Protection
Operating System Concepts – 9th Edition 8.4 Silberschatz, Galvin and Gagne ©2013
Address Binding
Programs on disk, ready to be brought into memory to execute form an input
queue
Without support, must be loaded into address 0000
Inconvenient to have first user process physical address always at 0000
How can it not be?
Further, addresses represented in different ways at different stages of a
program’s life
Source code addresses usually symbolic
Compiled code addresses bind to relocatable addresses
i.e. “14 bytes from beginning of this module”
Linker or loader will bind relocatable addresses to absolute addresses
i.e. 74014
Each binding maps one address space to another
Operating System Concepts – 9th Edition 8.5 Silberschatz, Galvin and Gagne ©2013
Binding of Instructions and Data to Memory
Operating System Concepts – 9th Edition 8.6 Silberschatz, Galvin and Gagne ©2013
Multistep Processing of a User Program
Operating System Concepts – 9th Edition 8.7 Silberschatz, Galvin and Gagne ©2013
Logical vs. Physical Address Space
Operating System Concepts – 9th Edition 8.8 Silberschatz, Galvin and Gagne ©2013
Memory-Management Unit (MMU)
Hardware device that at run time maps virtual to physical
address
Many methods possible, covered in the rest of this chapter
To start, consider simple scheme where the value in the
relocation register is added to every address generated by a
user process at the time it is sent to memory
Base register now called relocation register
MS-DOS on Intel 80x86 used 4 relocation registers
The user program deals with logical addresses; it never sees the
real physical addresses
Execution-time binding occurs when reference is made to
location in memory
Logical address bound to physical addresses
Operating System Concepts – 9th Edition 8.9 Silberschatz, Galvin and Gagne ©2013
Dynamic relocation using a relocation register
Operating System Concepts – 9th Edition 8.10 Silberschatz, Galvin and Gagne ©2013
Swapping
A process can be swapped temporarily out of memory to a
backing store, and then brought back into memory for continued
execution
Total physical memory space of processes can exceed
physical memory
Backing store – fast disk large enough to accommodate copies
of all memory images for all users; must provide direct access to
these memory images
Roll out, roll in – swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and executed
Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped
System maintains a ready queue of ready-to-run processes
which have memory images on disk
Operating System Concepts – 9th Edition 8.11 Silberschatz, Galvin and Gagne ©2013
Swapping (Cont.)
Does the swapped out process need to swap back in to same
physical addresses?
Depends on address binding method
Plus consider pending I/O to / from process memory space
Modified versions of swapping are found on many systems (i.e.,
UNIX, Linux, and Windows)
Swapping normally disabled
Started if more than threshold amount of memory allocated
Disabled again once memory demand reduced below
threshold
Operating System Concepts – 9th Edition 8.12 Silberschatz, Galvin and Gagne ©2013
Schematic View of Swapping
Operating System Concepts – 9th Edition 8.13 Silberschatz, Galvin and Gagne ©2013
Context Switch Time including Swapping
Operating System Concepts – 9th Edition 8.14 Silberschatz, Galvin and Gagne ©2013
Context Switch Time and Swapping (Cont.)
Operating System Concepts – 9th Edition 8.15 Silberschatz, Galvin and Gagne ©2013
Contiguous Allocation
Main memory must support both OS and user processes
Limited resource, must allocate efficiently
Contiguous allocation is one early method
Main memory usually into two partitions:
Resident operating system, usually held in low memory with
interrupt vector
User processes then held in high memory
Each process contained in single contiguous section of
memory
Operating System Concepts – 9th Edition 8.16 Silberschatz, Galvin and Gagne ©2013
Contiguous Allocation (Cont.)
Relocation registers used to protect user processes from each
other, and from changing operating-system code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each
logical address must be less than the limit register
MMU maps logical address dynamically
Can then allow actions such as kernel code being transient
and kernel changing size
Operating System Concepts – 9th Edition 8.17 Silberschatz, Galvin and Gagne ©2013
Hardware Support for Relocation and Limit Registers
Operating System Concepts – 9th Edition 8.18 Silberschatz, Galvin and Gagne ©2013
Multiple-partition allocation
Multiple-partition allocation
Degree of multiprogramming limited by number of partitions
Variable-partition sizes for efficiency (sized to a given process’ needs)
Hole – block of available memory; holes of various size are scattered
throughout memory
When a process arrives, it is allocated memory from a hole large enough to
accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
Operating System Concepts – 9th Edition 8.19 Silberschatz, Galvin and Gagne ©2013
Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
First-fit and best-fit better than worst-fit in terms of speed and storage
utilization
Operating System Concepts – 9th Edition 8.20 Silberschatz, Galvin and Gagne ©2013
Fragmentation
External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
Internal Fragmentation – allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used
First fit analysis reveals that given N blocks allocated, 0.5 N
blocks lost to fragmentation
1/3 may be unusable -> 50-percent rule
Operating System Concepts – 9th Edition 8.21 Silberschatz, Galvin and Gagne ©2013
Fragmentation (Cont.)
Operating System Concepts – 9th Edition 8.22 Silberschatz, Galvin and Gagne ©2013
Segmentation
Memory-management scheme that supports user view of memory
A program is a collection of segments
A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
Operating System Concepts – 9th Edition 8.23 Silberschatz, Galvin and Gagne ©2013
User’s View of a Program
Operating System Concepts – 9th Edition 8.24 Silberschatz, Galvin and Gagne ©2013
Logical View of Segmentation
4
1
3 2
4
Operating System Concepts – 9th Edition 8.25 Silberschatz, Galvin and Gagne ©2013
Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>,
Operating System Concepts – 9th Edition 8.26 Silberschatz, Galvin and Gagne ©2013
Segmentation Architecture (Cont.)
Protection
With each entry in segment table associate:
validation bit = 0 illegal segment
read/write/execute privileges
Protection bits associated with segments; code sharing
occurs at segment level
Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
A segmentation example is shown in the following diagram
Operating System Concepts – 9th Edition 8.27 Silberschatz, Galvin and Gagne ©2013
Segmentation Hardware
Operating System Concepts – 9th Edition 8.28 Silberschatz, Galvin and Gagne ©2013
Paging
Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
Avoids external fragmentation
Avoids problem of varying sized memory chunks
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and
load program
Set up a page table to translate logical to physical addresses
Backing store likewise split into pages
Still have Internal fragmentation
Operating System Concepts – 9th Edition 8.29 Silberschatz, Galvin and Gagne ©2013
Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit
Operating System Concepts – 9th Edition 8.30 Silberschatz, Galvin and Gagne ©2013
Paging Hardware
Operating System Concepts – 9th Edition 8.31 Silberschatz, Galvin and Gagne ©2013
Paging Model of Logical and Physical Memory
Operating System Concepts – 9th Edition 8.32 Silberschatz, Galvin and Gagne ©2013
Paging Example
Operating System Concepts – 9th Edition 8.33 Silberschatz, Galvin and Gagne ©2013
Paging (Cont.)
Calculating internal fragmentation
Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
Worst case fragmentation = 1 frame – 1 byte
On average fragmentation = 1 / 2 frame size
So small frame sizes desirable?
But each page table entry takes memory to track
Page sizes growing over time
Solaris supports two page sizes – 8 KB and 4 MB
Process view and physical memory now very different
By implementation process can only access its own memory
Operating System Concepts – 9th Edition 8.34 Silberschatz, Galvin and Gagne ©2013
Free Frames
Operating System Concepts – 9th Edition 8.35 Silberschatz, Galvin and Gagne ©2013
Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page
table
In this scheme every data/instruction access requires two
memory accesses
One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)
Operating System Concepts – 9th Edition 8.36 Silberschatz, Galvin and Gagne ©2013
Implementation of Page Table (Cont.)
Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access
next time
Replacement policies must be considered
Some entries can be wired down for permanent fast
access
Operating System Concepts – 9th Edition 8.37 Silberschatz, Galvin and Gagne ©2013
Associative Memory
Operating System Concepts – 9th Edition 8.38 Silberschatz, Galvin and Gagne ©2013
Paging Hardware With TLB
Operating System Concepts – 9th Edition 8.39 Silberschatz, Galvin and Gagne ©2013
Effective Access Time
Associative Lookup = time unit
Can be < 10% of memory access time
Hit ratio =
Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative
registers
Consider = 80%, = 20ns for TLB search, 100ns for memory access
Effective Access Time (EAT)
EAT = (1 + ) + (2 + )(1 – )
=2+–
Consider = 80%, = 20ns for TLB search, 100ns for memory access
EAT = 0.80 x 100 + 0.20 x 200 = 120ns
Consider more realistic hit ratio -> = 99%, = 20ns for TLB search,
100ns for memory access
EAT = 0.99 x 100 + 0.01 x 200 = 101ns
Operating System Concepts – 9th Edition 8.40 Silberschatz, Galvin and Gagne ©2013
Valid (v) or Invalid (i) Bit In A Page Table
Operating System Concepts – 9th Edition 8.41 Silberschatz, Galvin and Gagne ©2013
Shared Pages
Shared code
One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems)
Similar to multiple threads sharing the same process space
Also useful for interprocess communication if sharing of
read-write pages is allowed
Private code and data
Each process keeps a separate copy of the code and data
The pages for the private code and data can appear
anywhere in the logical address space
Operating System Concepts – 9th Edition 8.42 Silberschatz, Galvin and Gagne ©2013
Shared Pages Example
Operating System Concepts – 9th Edition 8.43 Silberschatz, Galvin and Gagne ©2013
Structure of the Page Table
Memory structures for paging can get huge using straight-
forward methods
Consider a 32-bit logical address space as on modern
computers
Page size of 4 KB (212)
Page table would have 1 million entries (232 / 212)
If each entry is 4 bytes -> 4 MB of physical address space /
memory for page table alone
That amount of memory used to cost a lot
Don’t want to allocate that contiguously in main memory
Hierarchical Paging
Operating System Concepts – 9th Edition 8.44 Silberschatz, Galvin and Gagne ©2013
Hierarchical Page Tables
Operating System Concepts – 9th Edition 8.45 Silberschatz, Galvin and Gagne ©2013
Two-Level Page-Table Scheme
Operating System Concepts – 9th Edition 8.46 Silberschatz, Galvin and Gagne ©2013
Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
Operating System Concepts – 9th Edition 8.47 Silberschatz, Galvin and Gagne ©2013
Address-Translation Scheme
Operating System Concepts – 9th Edition 8.48 Silberschatz, Galvin and Gagne ©2013
64-bit Logical Address Space
Operating System Concepts – 9th Edition 8.49 Silberschatz, Galvin and Gagne ©2013
Three-level Paging Scheme
Operating System Concepts – 9th Edition 8.50 Silberschatz, Galvin and Gagne ©2013