UNIT-2

INTRODUCTION TO THE ARM

INSTRUCTION SET
 Content
ARM Instruction Set:
 Data Processing Instructions
Addressing Modes
Branch
Load, Store Instructions
PSR Instructions
Conditional Instructions
ARM INSTRUCTION SET
Arm instruction set can be categorized into three
groups
1.DATA PROCESSING INSTRUCTIONS
2.DATA TRANSFER INSTRUCTIONS
3.CONTROL FLOW INSTRUCTIONS
Data Processing Instructions
• The data processing instructions manipulate data within
registers.
• They are move instructions, arithmetic instructions, logical
instructions, comparison instructions, and multiply
instructions.
• Most data processing instructions can process one of their
operands using the barrel shifter.
• If you use the S suffix on a data processing instruction, then
it updates the flags in the cpsr.
Move Instructions
Move is the simplest ARM instruction. It copies N into a
destination register Rd,
Where N is a register or immediate value. This instruction is
useful for setting initial values and transferring data between
registers.
ARITHMETIC INSTRUCTIONS
• The arithmetic instructions implement addition and
subtraction of 32-bit signed and unsigned values.
LOGICAL INSTRUCTIONS
Logical instructions perform bitwise logical
operations on the two source registers.
Comparison Instructions
The comparison instructions are used to compare or
test a register with a 32-bit value.

They update the cpsr flag bits according to the result,

but do not affect other registers.

After the bits have been set, the information can then
be used to change program flow by using conditional
execution.
Comparison Instructions
 Comparison Instructions

• They update the cpsr flag according to the result but do not
affect other registers

• CMP is effectively a subtract instruction with result discarded

• TST is logical AND operation

• TEQ is logical EOR

 MULTIPLY INSTRUCTIONS

The Basic ARM provides two multiplication instructions.

Multiply
MUL{<cond>}{S} Rd, Rm, Rs ; Rd = Rm * Rs

Multiply Accumulate - does addition for free

MLA{<cond>}{S} Rd, Rm, Rs,Rn ; Rd = (Rm * Rs) + Rn
MLA : Multiply Accumulate
MLA is used to multiply registers (signed or unsigned) to
create a 32 bit result, which is then added to another value,
which produces the final result.

Operand 2 is multiplied by operand 3, the value of operand 4 is

added, and the result is stored in operand 1. All operands
are registers.
 MLA : Example

MOV R1, #5

MOV R2, #3

MOV R3, #18

MLA R0, R1, R2, R3 ; R0 now equals 33

The Barrel Shifter
The ARM doesn’t have actual shift instructions.

Instead it has a barrel shifter which provides a

mechanism to carry out shifts as part of other
instructions.

So what operations does the barrel shifter support?

 Barrel Shifter
Rn Rm

processing
Pre-
processing
No pre-
• Shift the 32 bit binary
Barrel Shifter
pattern in one of the
source registers left or Result N
right by a specific
number of positions Arithmetic Logic Unit
before it enters the
ALU
Rd
Barrel Shift with Carry
 Barrel Shift with Carry Example
We apply a logical shift left (LSL) to register Rm before moving it to the
destination register.
 This is the same as applying the standard C language shift operator to the
register. TheMOV instruction copies the shift operator result N into register
Rd. N represents the result of the LSL operation
 PRE r5 = 5
 r7 = 8
 MOV r7, r5, LSL #2 ; let r7 = r5*4 = (r5 << 2)
 POST r5 = 5
 r7 = 20
 ARM Shift Operations
31 0 31 0

00000 00000

LSL #5 LSR #5

31 0 31 0

0 1

00000 0 1 1111 1

ASR #5 , positive operand ASR #5 , negative operand

31 0 31 0
C

C C

ROR #5 RRX
N Shift Operations Syntax
Immediate #immediate
Register Rm
Logical Shift Left by Immediate Rm, LSL #shift_imm
Logical Shift Left by Register Rm, LSL Rs
Logical Shift Right by Immediate Rm, LSR #shift_imm
Logical Shift Right by Register Rm, LSR Rs
Arithmetic Shift Right by Immediate Rm, ASR #shift_imm
Arithmetic Shift Right by Register Rm, ASR Rs
Rotate right by immediate Rm, ROR #shift_imm
Rotate right by register Rm, ROR Rs
Rotate right with extend Rm, RRX
Single Register Transfer
• Moving a single data item in and out of a register
• Data types supported are signed and unsigned words
(32 bit), half words (16 bit) and bytes
• <LDR|STR> {<cond>}{B} Rd,addressing
• <LDR> {<cond>}SB|H|SH Rd,addressing
• <STR> {<cond>}H Rd,addressing
Single Register Transfer
LDR load word into a register Rd <-mem32[address]

STR save byte or word from a register Rd ->mem32[address]

LDRB load byte into a register Rd <-mem8[address]

STRB save byte from a register Rd ->mem8[address]

LDRH load half word into a register Rd <-mem16[address]

STRH save half word from a register Rd ->mem16[address]

LDRSB load signed byte into a register Rd <-SignExtend

(mem8[address])

LDRSH load signed half word into a Rd <-SignExtend

register (mem16[address])
Single Register Load Store Addressing
Modes
• The ARM instruction set provides different modes for
addressing memory
• preindex with writeback
• preindex
• postindex
Index Methods
Index Data Base Example
Method Address
Register
preindex mem[base+offset] base+ LDR r0, [r1, #4]!
with offset
writeback
preindex mem[base+offset] not LDR r0, [r1, #4]
updated
postindex mem[base] base+ LDR r0, [r1], #4
offset
Index Methods
• Preindex with writeback calculates an address from a base
register plus address offset and then updates that address base
register with the new address.

• Preindex offset is same as the preindex with writeback but

does not update the address base register.

• Postindex only updates the address base register after the

address is used
 Multiple Register Transfer
• Load–store multiple instructions can transfer multiple
registers between memory and the processor in a single
instruction.
• Moving blocks of data around memory and saving and
restoring context stacks
• <LDM|STM>{<cond>}<addressing mode> Rn{!},<registers>{^}

LDM load multiple registers {Rd}*N <- mem32[start address +

4*N] optional Rn updated

STM save multiple registers {Rd}*N -> mem32[start address +

4*N] optional Rn updated
Addressing Mode for Load Store Multiple
Instructions
Add: Description Start End Rn!
Mode Address Address
IA increment after Rn Rn +4*N-4 Rn+4*N

IB increment before Rn + 4 Rn + 4*N Rn+4*N

DA decrement after Rn–4*N + 4 Rn Rn+4*N

DB decrement Rn – 4*N Rn - 4 Rn+4*N

before
Load Store Multiple pairs when base update used

Store Multiple Load Multiple

STMIA LDMDB
STMIB LDMDA
STMDA LDMIB
STMDB LDMIA
LDMIA
LDMIB
list of load-store multiple
instruction pairs
Addressing Methods for Stack Operations

Add: Description Pop =LDM Push =STM

Mode
FA full ascending LDMFA LDMDA STMFA STMIB

FD full descending LDMFD LDMIA STMFD STMDB

EA empty ascending LDMEA LDMDB STMEA STMIA

ED empty LDMED LDMIB STMED STMDA

descending
SWAP Instruction
• Swaps the contents of memory with the contents of a
register
• Atomic operation– it reads and writes a location in the
same bus operation,preventing any other instruction from
reading or writing to that location until it completes.
• SWP{B}{<cond>} Rd, Rm, [Rn]
SWAP Instruction
SWP swap a word between tmp=mem32[Rn]
memory and a register mem32[Rn]=Rm
Rd=tmp

SWPB swap a byte between tmp=mem8[Rn]

memory and a register mem8[Rn]=Rm
Rd=tmp
SWAP Instruction
A branch instruction changes the flow of execution or is used to call a routine.
This type of instruction allows programs to have subroutines, if-then-else
structures, and loops.

Branches are used to change execution flow.

The change of execution flow forces the program counter pc to point

to a new address.
The ARMv5E instruction set includes four different branch instructions.
Branch Instructions
B branch pc = label
BL branch with pc = label
link lr = address of the next inst. After BL
BX branch pc = Rm & 0xfffffffe,
exchange T = Rm & 1
BLX branch pc=label, T = 1
exchange with pc = Rm & 0xfffffffe,
link T = Rm & 1
lr = address of the next inst. After BL

The address label is stored in the instruction as a signed pc-relative offset and
must be within approximately 32 MB of the branch instruction. T refers to the
Thumb bit in the cpsr. When instructions set T, the ARM switches to Thumb
state.
Branch Instructions
Branch Instructions
Software Interrupt Instruction
• Causes a software interrupt exception
• Provides a mechanism to call OS routines
• SWI{<cond>} SWI_number

SWI lr_svc=address of instruction following

software the SWI
interrupt spsr_svc=cpsr
pc=vectors+0x8
cpsr mode =SVC
cpsr I = 1 (mask IRQ interrupts)
Since SWI instructions are used to call operating system routines, you
need some form of parameter passing. This is achieved using registers.
In this example, register r0 is used to pass the parameter 0x12. The
return values are also passed back via registers.
Code called the SWI handler is required to process the SWI call. The
handler obtains the SWI number using the address of the executed
instruction, which is calculated from the link register
Program Status Register
Instructions
• 2 instructions to directly control a psr
• MRS - transfers the contents of cpsr or spsr into a
register
• MSR - transfers the contents of register into cpsr
or spsr

Flags[24:31] Status[16:23] Extension[8:15] Control[0:7]

Fields
Bit 31 30 29 28 7 6 5 4 0

NZ CV I F T Mode
Function Condition Flags Interrupt Processor Mode
Masks
Thumb State
Program Status Register
Instructions
• MRS{<cond>} Rd,<cpsr|spsr>
• MSR{<cond>} <cpsr|spsr>_<fields>,Rm
• MSR{<cond>} <cpsr|spsr>_<fields>,#immediate

MRS copy psr to a gpr Rd = psr

MSR move gpr to a psr psr[field] = Rm

MSR move an immediate value psr[field] = immediate

to a psr
Coprocessor Instructions
• Are used to extend the instruction set
• Additional computation capability
• Used to control the memory subsystem
• Used only cores with a coprocessor
• CDP{<cond>} cp,opcode1,Cd,Cn{,opcode2}
• <MRC|MCR>{<cond>} cp, opcode1, Rd, Cn, Cm{,
opcode2}
• <LDC|STC>{<cond>} cp, Cd, addressing
Coprocessor Instructions
• cp field represents the coprocessor number between
p0 and p15
• opcode fields describe the operation to take place on
the coprocessor
• Cn, Cm and Cd describe registers within the
coprocessor
• CP15 – system control purposes
• MRC p15, 0, r10, c0, c0, 0
Coprocessor Instructions
CDP coprocessor data processing -perform an
operation in a coprocessor
MRC MCR coprocessor register transfer –move data
to/from coprocessor registers

LDC coprocessor memory transfers –load and

store blocks of memory to/from a
STC coprocessor
Loading Constants
• LDR Rd, =constant
• ADR Rd, label
LDR Load constant Rd = 32 bit constant
pseudoinstruction
ADR Load address Rd = 32 bit relative
pseudoinstruction address
Loading Constants
Pseudo instruction Actual instruction

LDR r0, =0xff MOV r0, #0xff

LDR r0, =0x55555555 LDR r0, [pc,#offset_12]

Count Leading Zeroes Instruction

• CLZ
• Counts the number of zeroes between the MSB and
the first bit set to 1
– R1=0x00000010
– CLZ R0,R1
– R0 = 6
Conditional Execution
• The instruction only executes if the condition code
flags pass a given condition or test
• Increase performance & code density
• 2 letter mnemonic (eg: AL) or always execute.
• Conditional execution depends on
– Condition field
– Condition flags
Summary
• All ARM instructions are 32 bit in length
• Arithmetic, logical, comparison & move
instructions can all use the inline barrel shifter
• 3 types of load store instruction – single register,
multiple register, swap
• SWI & Program Status Register
• ARMv5E –CLZ, saturation, improved multiply
instructions
• Conditional execution