INSTRUCTION FORMAT: An instruction is a command to the microprocessor to perform a given task on specified data.

. each instruction has two parts: one is the task to be performed, called the operation code (opcode) and the 2nd is the data to be oeprated on called operand. The operand can be specified in various ways. It may include 8 bit (n 16 bit) data, an interval register memory location or 8 bit (n 16 bit) address.

Opcode

Operand(s)

8085 instruction can be classified into three groups according to word size. (1) One word or 1-byte instruction (2) Two word or 2-byte instruction . (3) Three word or 3-byte instruction.

1-byte instruction: A 1-byte instruction includes the opcode and the operand in the same byte. these instruction need one memory location in memory. Example: MOV C, A Copy the contents of Account to C register. ADD B Add the contents of B to Account Contents. CMA Complement the contents of Account. 2-byte instruction: In a 8-byte instruction the 1st byte is opcode and the 2nd byte is operand. These instruction need two memory location in memory.

3-byte instruction: In a 3-byte instruction the 1st byte specifies the opcode, following two bytes specifies 16 bit address. Note that 2nd byte lower order address and 3rd byte is higher order address. These instruction need 3 memory location. Example: JMP 4500.

DATA TRANSFER OPERATIONS

The data transfer instructions copy data from a source into a destination without modifying the contents of the source. The previous contents of the destination are replaced by the contents of the source.

INTEL 8085 INSTRUCTION SET

GROUP-I: DATA TRANSFER INSTRUCTIONS 1. MOV Rd, Rs (Rd) (Rs) The content of source register (Rs) is moved to destination register (Rd). The registers Rd and Rs can be anyone of the general purpose registers: A, B, C, D, E, H and L. No flags are affected. Example: MOV B, C. (B) (C) 1-byte instructions Register Addressing 1-machine cycle - opcode fetch 4T states Total No. of instructions = 49.

2. MOV Rd, Pm (Rd) (M) or (Rd) ((HL)) The content of memory (m) addressed by H-L pair is moved to destination register (Rd).The register Rd can be any one of te general purpose registers A, B, C, D, E, H, and L. No flags are affected. Example: MOV A, M (A) <-- (M) or (A) ((HL)) * Register indirect addressing * 1 byte instruction * 2 machine cycles opcode fetch 4 T memory read 3 T Total no of T states -- 7 T * Total No. of instructions = 7.

3. MVI Rd, d8 (Rd) d8 The 8-bit data (d8) in the instruction is moved to destination register (Rd). The register Rd can be any one of the general purpose registers, A, B, C, D, E, H and L. No flags are affected. Example: MVI D, 09 (D) 09 The 8-bit data 09H in the instruction is moved to D-register. * Immediate addressing * 2-byte instruction 2-machine cycles opcode fetch 4 T memory read 3 T * Total No. of instruction = 7. 4. MOV M, Rs (m) (Rs) or ((HL)) (Rs) The content of source register (Rs) is moved to memory location addressed by HL pair. The register Rs can be any one of the general purpose register A, B, C, d, E, H and L. No flags are affected. Example: MOV M, B (M) (B) or ((HL)) (B) The content of B-register is moved to memory location addressed by HL pair. *Register Indirect addressing * 1-byte instruction * 2-machine cycles opcode fetch 4 T memory write 3 T Total No. of instructions = 7

ARITHMETIC INSTRUCTIONS
These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement. 1. ADD reg. (A) <-- (A) + (reg) The content of the register is added to the content accumulator (A-register). After addition the result will be in accumulator. All flags are affected the register can be any one of the general purpose register A, B, C, D, E, F, H and L. Example: ADD E A <-- A + r The content of E-register is added to the content of A-register. The result will be in A register. ADD A , ADD C ,ADD E, ADD L,ADD B, ADD D, ADD H.

2. ADI d8 (A) <-- (A) + d8 The 8-bit data in the instruction is added to the content of A-register (Accumulator). After addition the result will be in accumulator. All flags are affected. Immediate Addressing. 2-byte instruction. 3. ADD M (A) (A) + (M) or (A) (A) + ((HL)) The content of memory addressed by HL pair is added to the content of A-register. After addition the result will be in A-register. All flags are affected. Example: ADD M Let the content of A be 44H. Let the content of HL be C00AH. Let the content of memory location C00AH be 73H The content of the memory location C00AH is added to the content of A-register. The result is put back in A-register. Register Indirect Addressing 1-byte, Instruction 2-machine cycles Opcode fetch 4 Memory Read 3 T Total No. of instruction = 1.

4 .ADC reg. (A) <-- (A) + (reg) + CY The content of the register and the carry flag are added to the content of the A-register. After addition the result will be in A-register. All flags are affected. The register can be anyone of the general purpose register A, B, C, D, E, H and L. Example: ADC H (A) + (H) + CY (A) Register Addressing 1-byte Instruction 1-machine cycle-opcode fetch 4 T Total No. of instructions = 7. ADC A ADC C ADC E ADC L ADC B ADC D ADC H. 5.ACI d8 (A) (A) + d8 + CY The 8-bit data in the instruction and the carry flag (the value of carry flag before executing this instruction) are added to the content of A-register (Accumulator). After addition the result will be in accumulator. All flags are affected. Immediate Addressing. 2-byte instruction. 2-machine cycles Opcode fetch 4 T Memory read 3 T Total No. of instruction = 1.

6. ADC M (A) <-- (A) + (M) + CY or (A) (A) + ((HL)) + CY The content of memory address by HL pair and the value of carry flag (before executing this instruction) are added to the content of A-register. After addition the result will be in A register. All flags are affected. Register Indirect Addressing. 1-byte instruction. 2-machine cycles - Opcode fetch 4 T Memory read 3 T Total o. of instruction = 1. 7. SUB reg. (A) (A)-(reg) The content of the register is subtracted from the content or the accumulator (A-register). After subtraction the result will be in A-register. All flags are afected. The register can be anyone of the general purpose register A, B, C, D, E, H and L. Register Addressing 1-byte instruction 1-machine cycle opcode fetch 4 T Total No. of instructions = 7 SUB A ,SUB C, SUB E, SUB L, SUB B, SUB D, SUB H.

8. SUI d8 (A) d8 (A) The 8-bit data given in the instruction is subtracted from A-register (accumulator). After substraction the result will be in A-register. All flags are affected. Immediate Addressing 2-byte instruction 2-machine cycle Opcode fetch 4 T Memory Read 3 T Total No. of instruction = 1. 9. SUB M (A) <--(A)- (M) or (A) (A) - ((HL)) The content of memory addressed by HL pair is subtracted from A-register. After subtraction the result will be in A-register. All flags are affected. Register Indirect Addressing 1-byte instruction 2-machine cycles Opcode fetch 4 T Memory Read 3 T Total No. of instruction = 1.

10.SBB reg (A) (A) (reg) CY The content of register and the value of carry (before executing this instruction) are subtracted from accumulator. After subtraction the result will be in accumulator. All flags are affected. The register can be anyone of the general purpose register A, B, C, D, E, H and L. Register Addressing. 1-byte Instruction. 1-machine Cycle Opcode fetch 4 T Total No. of instruction = 7. SBB A SBB C SBB E SBB L SBB B SBB D SBB H 11. SBI d8 (A) (A) d8 CY The 8-bit data in the instruction and the values of carry (before executing this instruction) are subtracted from accumulator. After subtraction the result will be in accumulator. All flags are affected. Immediate Addressing 2-byte instruction 2-machine cycles Opcode fetch 4 T

12. SBB M (A) (A) (M) CY or (A) (A) ((HL)) CY The content of memory addressed by the and the value of carry (before executing this instruction) are subtracted from accumulator (A-register). After subtraction the result will be in A-register. All flags are affected. Register Indirect Addressing 1-byte instruction. 13.SBB reg (A) (A) (reg) CY The content of register and the value of carry (before executing this instruction) are subtracted from accumulator. After subtraction the result will be in accumulator. All flags are affected. The register can be anyone of the general purpose register A, B, C, D, E, H and L. Register Addressing. 1-byte Instruction. 1-machine Cycle Opcode fetch 4 T Total No. of instruction = 7. SBB A SBB C SBB E SBB L SBB B SBB D SBB H

14. SBI d8 (A) (A) d8 CY The 8-bit data in the instruction and the values of carry (before executing this instruction) are subtracted from accumulator. After subtraction the result will be in accumulator. All flags are affected. Immediate Addressing 2-byte instruction 2-machine cycles Opcode fetch 4 T Memory Read 3 T Total No. of instruction = 1. 15. SBB M (A) (A) (M) CY or (A) (A) ((HL)) CY The content of memory addressed by the and the value of carry (before executing this instruction) are subtracted from accumulator (A-register). After subtraction the result will be in A-register. All flags are affected. Register Indirect Addressing 1-byte instruction 2-machine cycles Opcode fetch 4 T Memory Read 3 T Total No. of instruction = 1.

16.DAD rp DAD Double Addition (HL) (HL) + (rp) The content of register pair is added to the content of HL pair. After addition the result will be in HL pair. Only carry flag is affected. The register pair can be BC, DE, HL or SP. Register addressing. 1-byte instruction. 3-machine cycles Opcode fetch 4 T Bus Idle 3 T Bus Idle 3 T Total No. of instructions = 4. DAD B DAD H DAD D DAD SP 17. DAA DAA Decimal Adjust Accumulator After BCD addition, this instruction is executed to get the result in BCD when DAA instruction is executed the content of the accumulator is altered or adjusted as explained below. (i) If the sum of lower nibbles exceeds 09H or auxillary carry is set, a correction 06H (0111) is added to lower nibble. (ii) If the sum of upper nibbles exceeds 09H or carry is set, a correction 06H (0111) is added to upper nibble. After executing this instruction all flags are affected.

18. INR reg. (reg) <--(reg) + 01 The content of the register is incremented by one. Except carry flag, all other flags are affected. The register can be any one of the general purpose register A, B, C, D, E, H and L. Example: INR B (B) <-- (B) + 01 Register Addressing, 1-byte instruction, Total No. of instructions = 7. 1-machine cycle, Opcode fetch 4 T INR A INR C INR D INR L INR B INR D INR H 19. INR M (M) <-- (M) + 1 or ((HL)) ((HL)) + 1 The contnet of memory addressed by the pair is incremented by one. Except carry, all other flags are affected. Example: INR M Register Indirect Addressing 1-byte instruction 3-machine cycles Opcode fetch 4 T Memory Read 3 T Memory Write 3 T Total No. of instruction = 1.

17. DCR reg. (reg) <-- (reg) - 01. The content of the register is decremented by one except carry all other flags are affected the register can be A, B, C, D, E, H or L. Example: DCR D (D) <-- (D)-- 01 The content of D register is decremented by one. Register Addressing. 1-byte instruction. 1-machine cycle-opcode fetch 4.7 Total No. of instructions = 7. DCR A DCR C DCR E DCR L DCR B DCR D DCR H. 18. DCR M (M) <-- (M)-- 01 or ((HL)) ((HL)) --01. The content of memory addressed by HL pair is decremented by one. Except carry all other flags are affected. Example: DCR M Register indirect Addressing 1-byte instruction. 3-machine cycles Opcode fetch 4 T Memory Read 3 T

19. INX rp (rp) <-- (rp) + 01 The content of register-pair is incremented by one. The register pair can be BC, DE, HL or SP. No flags are affected. Example: INX H (HL) <- (HL) + 01 The content of the pair is incremented by one. Register Addressing 1-byte instruction 1-machine cycle Opcode fetch 6 T. Total No. of instructions = 4 INX B INX D INX H INX SP. 20. DCX rp (rp) (rp) - 01 The content of register pair is decremented by one the register-pairs can be BC, DE HC or SP. No flags are affected. Example: DCX SP (SP) <- (SP) - 01 The content of stack pointer is decremented by one. Register Addressing 1-byte instruction DCX B DCX D DCX H DCX SP.

GROUP - III: LOGICAL INSTRUCTIONS

1. ANA reg. (A) ' (reg) (A) The content of the register is logically ANDed with the content of accumulator. The register can be any one of the general purpose register A, B, C, D, E, H and L. After execution of the instruction carry flag is reset and auxillary carry flag is set. Other flags are altered (according to the result). After AND operation results will be in accumulator. Example: ANA E (A) ' (E) (A) The content of E-register is logically ANDed with the content of accumulator. Before execution AND operation After execution Register addressing 1-byte instruction 1-machine cycle-opcode fetch - 4 T Total No. of instructions = 7. ANA A, ANA D ,ANA H,ANA B ,ANA E, ANA L,ANA C.

2. ANI d8 (A) ' d8 (A) The 8-bit data in the instruction is logically ANDed with the content of accumulator. The result will be in accumulator. After execution of this instruction CF = 0 and AC = 1. Other flags are affected. Immediate addressing. 2-byte instruction. 2-machine cycles - Opcode Fetch 4 T. 3. ANA M (A) <-- (A) ' (M) or (A) (A) ' ((HL)). The content of memory addressed by HL pair is logically ANDed with the content of accumulator. The result will be in accumulator. After execution CF = 0 and AC = 1. Other flags are affected. Example ANA M. Let the content of HL = 105AH. Let the content of memory location 105A = 4 C. The content of memory location 105AH is logically ANDed width the content of accumulator. The result will be in accumulator. Register Indirect Addressing. 1-byte instruction. 2-machine cycles Opcode fetch 4 T Memory Read 3 T Total No. of instruction = 1.

4. ORA reg. (A) <-- (A) ( (reg) The content of the register is logically ORed with the content of accumulator. The result will be in accumulator the register can be any one of the general purpose register A, B, C, D, E, H and L. After execution of the instruction both the carry and auxiliary flags are reset (AC = 0, CY = 0). Other flags are affected (according to the result). Example: ORA B (A) (A) (B) The content or B-register is logically ORed with the content of accumulator. Register Addressing 1-byte instruction 1-machine cycle Opcode fetch 4 T Total No. of instructions = 7. ORA A ORA D ORA H ORA B ORA E ORA L ORA C 5. ORI d8 (A) <--(A) ( d8) The 8-bit data in the instruction is logically ORed with the content of accumulator. The result will be in accumulator. After execution of this instruction CF = AC = 0. Other flags are affected. Immediate Addressing 2-byte Instruction 2-machine cycles - Opcode fetch 4 T Memory Read 3 T Total No. of instruction = 1.

6.ORA M (A) (A) (M) or (A) (A) ((HL)) The content of memory addressed by HL pair is logically ORed with the content of accumulator. The result will be in accumulator. After execution CF = AC = 0. Other flags are affected. Example: ORA M Let the content of HL pair = 2050H. Let the content of memory location 2050H is = 1B. The content of memory location 2050 is logically ORed with the content of accumulator. The result will be in accumulator. Register Indirect Addressing 1-byte Instruction 2-machine cycles Opcode fetch 4 T Memory Read 3 T Total no. of instruction = 1. 7. XRA reg (A) (A) (reg). The content of the register is logically EXCLUSIVE ORed with the content of accumulator. The result will be in accumulator. The registers can be anyone of the general purpose register A, B, C, D, E, H and L. After execution AC = CY = 0. Other flags are affected (according to the result). Example: XRA A (A) (A) (A) The content of A register is EXCLUSIVE-ORed with the content of A register itself. Register Addressing 1-byte instruction 1-machine cycle Opcode fetch 4 T.

8. XRI d8 (A) (A) + d8 The 8-bit data in the instruction is logically EXCLUSIVE-ORed with the content of accumulator. The result will be in accumulator. After execution of this instruction CF = AF = 0. Other flags are affected. Immediate addressing 2-byte instruction 2-machine cycles Opcode fetch 4 T Memory read 3 T Total No. of instruction = 1. 9. XRA M (A) <-- (A) +(M) or (A) (A)+ ((HL)) The content or memory addressed by HL pair is logically EXCLUSIVE-ORed with the content of accumulator. The result will be in accumulator. After execution CF = AC = 0. Other flags are affected. Example: XRA M Let the content of HL pair = 805AH. Let the content of memory location 805AH = C4. The content of memory location 805AH is logically EXCLUSIVE-ORed with the content of accumulator. The result will be in accumulator.

11.CMP reg (A) - (reg) . affects flags The content of the register is compared with accumulator. The comparison is performed by subtracting the data in the ALU but the result is discarded, only the flags are altered.After execute of the instruction the content of accumulator and the register are not altered. All flags are affected by this instruction. The following three condition may arise after execution of compare instruction. (i) If (A) < (reg) then carry fla gis set (CY = 1) (ii) If (A) > (reg) then carry flag is reset or cleared (CY = 0) (iii) If (A) = (reg) then zero flag is set (ZF = 1) The register can be any one of the general purpose register A, B, C, D, E, H and L. Example: CMP B (A) (B) . affects flags. The content of B-register is compared with accumulator. The comparison is performed by subtracting the content of B-reg from the content of accumulator in the (ALU) but the result is discarded, only the flags are altered. The contents of the accumulator and the Bregister and not altered. Register addressing 1-byte instruction 1-machine cycle Opcode fetch 4 T Total No. of instruction = 7. CMP A CMP D CMP H CMP B CMP E CMP L CMP C

11. CPI d8 (A) - d8 . affects flags. The 8-bit data in the instruction is compared with accumulator. The comparison is performed by subtracting the data in the ALU, but the result is discarded, only the flags are altered. After execution of the instruction the content of accumulate is not altered. All flags are affected. The following three condition may arise after execution of this instruction. (i) If (A) < d8 then carry flag is set (CY = 1). (ii) If (A) > d8 then carry flag is resent or cleared (CY = 0). (iii) If (A) = d8 then zero flag is set (ZF = 1). Immediate Addressing 2-byte instruction 2-machine cycles Opcode fetch 4 T Memory Read 3 T Total No. of instruction = 1.

12.CMP M (A) - (M) affects flags or (A) ((HL)) The content of memory addressed by HL pair is compared with accumulator. The comparison is performed by subtracting the datas in ALV, but the result is discarded, only the flag, are altered. After execution of the instruction the content or the accumulator and the memory are not altered. All flags are affected by this instruction. The following three condition may arise after execution of this instruction. (i) If (A) < (m) then carry flag is set (CY = 1). (ii) If (A) > (m) then carry flag is reset or cleared (CY = 0). (iii) If (A) = (m) then zero flag is set (ZF = 1). Example: CMP M Let the content of HL pair = C050H. Let the content of memory lcoation C050H = 7AH The content of memory location C050 is compared with the content of accumulator. Only flags are altered. The content of accumulator and the memory remains same. Register Indirect addressing 1-byte instruction 2-machine cycles Opcode fetch 4 T Memory Read 3 T Total No. of instruction = 1.

13. CMA CMA Complement Accumulator. AA The content of accumulator is complemented. Implied addressing. 1-byte Instruction. 1-machine cycle Opcode fetch 4 T.

14. STC STC Set Carry The carry flag is set to 1. Only carry flag is affected by this instruction. Implied Addressing 1-byte instruction 1-machine cycle Opcode fetch 4 T. 15. CMC CMC Complement Carry The carry flag is complemented Only carry flag is affected by this instruction. Implied Addressing 1-byte instruction 1-machine cycle Opcode fetch 4 T. 16. RLC RLC Rotate Accumulator Left to carry. The content of A-register is rotated left by one bit and the left most bit of A-register is rotated to carry. [The left most bit is most significant bit]. Implied Addressing 1-byte instruction 1-machine cycle Opcode fetch 4 T.

17. RRC RRC Rotate Accumulator Right to Carry. The content of A-register is rotated right by one bit and the right most bit of A-register is rotated to carry. [The right most bit is least significant bit]. Implied Addressing. 1-byte instruction. 1-machine cycle Opcode fetch 4 T. 18. RAR RRR Rotate Accumulator Right through Carry. The content of A-register along with carry is rotated right by one bit. Here the carry is moved most significant bit (D7) postiion and the least significant bit (D0) is moved to carry. Implied Addressing. 1-byte instruction. 1-machine cycle Opcode fetch 4 T. 19. RAL RAL Rotate Accumulator Left through Carry. The content of A-register along with carry is rotated left by one bit. Here the carry is moved to least significant bit (D0) position and the most significant bit (D7) is moved to carry. Implied Addressing. 1-byte instruction. 1-machine cycle Opcode fetch 4 T.

GROUP-IV BRANCHING INSTRUCTION Unconditional Jump Instruction:

1. JMP addr 16 (PC) addr 16 It is an unconditional jump instruction when this instruction is executed, the address given in the instruction is moved to program counter. Now the processor starts executing the instructions stored in this address. Direct Addressing 3-byte instruction 3-machine cycles - Opcode fetch 4 T Memory Read 3 T

2.Conditional Jump Instructions: A conditional jump instruction will check a flag condition. If the flag condition is true then the address given in the instruction is moved to program counter. Thus the program control is branched to jump address. If the flag condition is false, then the next instruction is executed. There are eight conditional jump instructions. JZ addr16 Jump on zero Jump if zero flag = 1 JNZ addr16 Jump on No-zero Jump if zero flag = 0 JC addr16 Jump on carry Jump if carry flag = 1 JNC addr16 Jump on No-carry Jump if carry flag = 0 JM addr16 Jump on minus Jump if sign flag = 1 JP addr16 Jump on positive Jump if sign flag = 0 JPE addr16 Jump on parity even Jump if parity flag = 1 JPO addr16 Jump on parity odd Jump if parity flag = 0. Direct addressing 3 byte instructions 2 or 3 machine cycles - Condition False Condition True Opcode fetch 4 T Opcode fetch 4 Memory Read 3 T Memory Read 3 Memory Read 3T

Unconditional Subroutine CALL: 3.CALL addr16 ((SP)) (PC) (M) (PC) (SP) (SP ) - 02 or (SP) <--(SP) - 02 (PC) <-- addr 16 (PC) <-- addr 16 It is unconditional CALL used to call a subroutine program. When this instruction is executed the address of the next instruction in the rogram is pushed to stack. The 16-bit address (which is the address of sub-routine program) given in the instruction is loaded in program counter. Now the processor will start executing the instruction stored in this call address. Direct Addressing. 3-byte instruction. 5-machine cycles Opcode fetch 6 T Memory Read 3 T Memory Read 3 T Memory Write 3 T Memory Write 3 T

4.Conditional Subroutine CALL: A conditional CALL instruction will check for a flag condition. If the flag condition is true, then the address of the next instruction is pushed to stack and the call address is loaded in program counter. Now the processor will start executing the instructions stored in this address. If the flag condition is false, then the next instruction is executed. There are eight conditional CALL instructions. CZ addr16 Call on Zero Call if Zero flag = 1 CNZ addr16 Call on No-zero Call if Zero flag = 0 CC addr16 Call on Carry Call if Carry flag = 1 CNC addr16 Call on No-carry Call if Carry flag = 0 CM addr16 Call on Minus Call if Sign flag = 1 CP addr16 Call on Positive Call if Sign flag = 0 CPE addr16 Call on Parity even Call if Parity flag = 1 CPO addr16 Call on Parity odd Call if Parity flag = 0 Direct Addressing 3-byte instruction 2 or 5 - Machine Cycles Flag condition False Flag condition True Opcode fetch 6 T Opcode fetch 6 T Memory Read 3 T Memory Read 3 T Memory Read 3 T Memory Write 3 T

5. RET RET Return to Main Program. (PC) ((SP)) or (PC) (M) This instruction is placed at the end of subroutine program, in order to return to the main program. When this instruction is executed the top of stack is poped to program counter. [Note: While calling the subroutine using CALL instruction, the return address of main program is pushed to stack. This return instruction RET pops that to program counter. Thus the processor resumes the execution of main program]. Register Indirect addressing 1-byte instruction 3-machine cycles Opcode fetch 4 T Memory Read 3 T Memory Read 3 T

6. Conditional Return: In a conditional return instruction a flag condition is tested. If the flag condition is true then the program control returns to main program by poping the top of stack to program counter. If the flag condition is false then the next instruction is executed. There are eight conditional return instructions. RZ Return on zero. Return if zero flag = 1. RNZ Return on No-zero. Return if zero flag = 0. RC Return on carry. Return if carry flag = 1. RNC Return on No. carry. Return if carry flag = 0. RM Return on Minus. Return if sign flag = 1. RP Return on Positive. Return if sign flag = 0. RPE Return on Parity Even. Return if parity flag = 1. RPO Return on Parity Old. Return if parity flag = 0. Register Indirect Addressing. 1-byte Instructions. 1 or 3 Machine Cycles Flag Condition False Flag Condition True Opcode fetch 6 T Opcode fetch 6 T Memory Read 3 T Memory Read 3 T

7.Restart Instructions: The restart instructions and also called as software interrupts. Each restart instruction has a vector address. The vector address is fixed by the manufacturer (INTEL). When a restart instruction is executed the content of program counter is pushed to stack and the vector address is loaded in the program counter. The vector address is internally computed by the processor. The vector address for RST n is obtained by multiplying n by 8. thus the program control is branched to a subroutine program stored in this vector address. There are eight restart instructions. RST 0 RST 1 RST 2 RST 3 RST 4 RST 5 RST 6 RST 7 1-byte instructions. 3-machine cycles Opcode fetch 6 % Memory write 3 T Memory write 3 T

Group V MACHINE CONTROL INSTRUCTIONS

1. DI (DI Disable Interrupts) When this instruction is executed all the interrupts except tags are disabled [when the interrupts are disabled the processor will not accept the interrupt, if an interrupt signal is applied through the interrupt pins]. [When the processor is doing an emergency work, it can execute DI instruction to prevent the interrupts from interrupting the processor]. One byte instruction One machine cycle - Opcode fetch - 4 T. 2. EI (EI Enable Interrupt) This instruction is used or executed to allow the interrupts after disabling. The interrupts except TRAP are disabled after processor reset or after execution of DI instruction. (when we want to allow the interrupts, we have to execute EI instructions). One byte instruction. One machine cycle - Opcode fetch - 4 T.

3. SIM (SIM Set Interrupt Mask) The SIM instruction is used to mask the hardware interrupts RST 7.5, RST 6.5 and RST 5.5. It is also used to send data through SOD line. (SOD-serial output data pin of 8085 processor). The execution of SIM instruction output the content of the accumulator to define interrupt mask bits and the serial output data line. The bits in the accumulator before exeuction of the SIM instruction are defined as shown in the figure below. If the mask set enable bit is set to one, interrupt mask bits for RST 7.5, RST 6.5 and RST 5.5 are sent out. A zero value at the mask set enable does not affect the interrupt mask bits. A one at a particular interrupt mask disables that interrupt and a zero enables it. The RESET RST 7.5 if set to one, resets an internal flip-flop to zero in order to disable the RST 7.5 interrupt.I f the serial output enable is one, the serial output data are sent to the SOD pin.

4. RIM (RIM Read Interrupt Mask) The RIM instruction is used to check whether an interrupt is masked or not. It is also used to read data from SID lines (SID - Serial Input Data pin or 8085 processor). When RIM instruction is executed the accumulator is loaded with 8-bit data. The 8bit data in the accumulator (content of accumulator) can be interpreted as shown in figure below. Bit D0, D1 and D2 provide, the values of the RST 5.5, RST 6.5 and RST 7.5 mask bits respectively. If the mask bit corresponding to a particular RST is one the interrupt is disabled. If the mask bit is zero then the interrupt is enabled. If the interrupt enable bit (D3) is 0, the 8085s markable interrupts are disabled. The interrupts are enabled if this bit is one. A one in a particular interrupt pending bit indicates that an interrupt is being requested on the identified RST line, if this bit is zero, no interrupt is waiting to be serviced. The serial input data (bit D7) indicate the value of the SID pin.

5. HLT (HLT Halt Program Execution) This instruction is placed at the end of the program, when this instruction is executed the processor suspends program execution and bus will be in idle state. Bit D0, D1 and D2 provide, the values of the RST 5.5, RST 6.5 and RST 7.5 mask bits respectively. If the mask bit corresponding to a particular RST is one the interrupt is disabled. If the mask bit is zero then the interrupt is enabled. If the interrupt enable bit (D3) is 0, the 8085s markable interrupts are disabled. The interrupts are enabled if this bit is one. A one in a particular interrupt pending bit indicates that an interrupt is being requested on the identified RST line, if this bit is zero, no interrupt is waiting to be serviced. The serialinput data (bit D7) indicate the value of the SID pin. 1-byte instruction. 2-machine cycle Opcode fetch 3 T Bus idle 2 T 5T
6. NOP (NOP No Operation) The NOP is a dummy instruction, it neither achieves any result nor affects any CPU registers. This is a useful instruction for producing software delay and reserve memory spaces for future software modifications.