JPS63133205A - Data input system for programmable controller - Google Patents

Abstract

PURPOSE:To eliminate the wrong data arithmetic operations by keeping the input data in a register until an instruction is executed based on this input data and therefore securing a sure reading action of a CPU even though the duration of data is shorter than the scan time. CONSTITUTION:The input data DATA 0-7 are read and kept by a register 1d based on the input of a strobe signal STRB and the register 1d clears its contents with input of a clear signal CLS. An FF1e is set by the input of the signal STRB to store that the input data is read and then reset with input of the signal CLS. Meanwhile an output signal BUSY is validated. A decoder 1c transmits a gate signal G based on the control signal sent from a control line 4 to actuate a register 1d and reads the output data with a CPU 2. In such a way, the input data is temporarily stored in the register 1d and then read by the CPU 2 when this unit receives an access.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a data input method for a programmable controller, and particularly relates to multi-bit data in which the duration (on time) of pulse-like data input is shorter than the scan time. The present invention relates to a new data input method suitable for input.

(Prior art) Figure 3 is a block diagram of a data input unit explaining this type of conventional system.
a) and an output gate (lb) for outputting the output signal of this interface (la) to a human output data bus (3) to be described later, and a control signal from a control line (4) to be described later, the unit is accessed. The gate signal G is used to determine whether the
(2) is the CPU of the programmable controller, (
3) is a CPU input/output data bus consisting of multiple bits,
(4) shows a CPU control line consisting of multiple bits.

Next, a conventional data input method according to the above configuration will be explained.

Data signals DATEO to DATE7 (in the case of 8-bit string) are always input to the output gate (1b) via the λ interface (1a), and when this unit (1) is accessed by the program of the CPU (2), ,
By the gate signal G from the decoder (IC), the input data is passed through the input/output data bus (3) via the output gate (1b).
) is output, read by CPIJ (2), and used for calculations.

Here, there is a close relationship between the input data duration (ON time) Td and the scan time Ts of the programmable controller, and as shown in FIG. 4, if the input data duration Td is greater than the scan time Ts, Input data can be read at all times during scanning; for example, if A in the figure is the execution timing of an instruction that uses data input to this unit for calculation, the input data will always exist and be read no matter what timing A is. be able to.

(Problems to be Solved by the Invention) However, as shown in FIG. 5, when the duration Td of the input data is shorter than the scan time Ts (Td<Ts), the following problem occurs. Medium timing A
At timing t, the data exists and can be read, but at timing A2, after the data duration ends, the data does not exist, and erroneous data (:PU (2) is read. will not be obtained.

In this way, a problem occurs when Td<Ts, which is a drawback of the conventional method. This drawback exists in programmable controllers that use a so-called direct method for input/output control, in which external input/output signals are accessed during instruction execution.

Therefore, the present invention was made to solve the problems in the conventional method as described above, and it is possible to reliably use the CPU even if the duration Td of input data is shorter than the scan time Ts.
The present invention provides a data input method for a programmable controller that can be read into a programmable controller.

[Means for solving problems]

The data input method of the programmable controller according to the present invention includes a register that reads and holds input data consisting of a plurality of bits based on the input of a strobe signal, and clears the memory contents based on the input of a clear signal, and the strobe signal. is set based on the input to enable the output signal and remember that the input data has been read;
The flip-flop is reset based on the input of the clear signal to invalidate the output signal, and the control line that controls the input/output data bus based on the CPU program determines when this is accessed and sends out a gate signal. It also includes a decoder that sends out the clear signal after the completion of the data output operation, and an output gate that outputs the output of the register to the input/output data bus based on the input of the gate signal, and outputs the input data to the strobe signal. At the same time, the strobe signal is stored in the above flip-flop and output to the outside, and when accessed by the program, a gate signal is generated from the above decoder and the output of the register is sent to the human output data bus. It is characterized in that the registers and flip-flops are reset by the decoder at the subsequent timing.

(Function) According to this invention, since data can be held in a register from the time it is input until the time when the instruction that requires it is executed, the data can be reliably read by the CPU even if the data duration is shorter than the scan time. be able to.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. In FIG. 1, the same symbols as in FIG. 3 indicate the same parts, and (l
d) is a register that reads and holds input data DATEO to DATE7 based on the input of the strobe signal 5TRB, and clears the stored contents based on the input of the clear signal CLS, which will be described later; (le) is the strobe signal 5T;
The flip-flop is set based on the input of RB to remember that the input data has been read, and is reset based on the input of the clear signal CLS, during which the output signal BtlSY is made valid. In addition, the decoder (1c)
determines when this unit is accessed based on the control signal from the control line (4), sends out the gate signal G, and outputs the output data Q0 to Q7 of the register (1d) through the output gate (1b). It is output to the input/output data bus (3) and read by the CPU (2), and the clear signal CLS is output at the timing after this data output operation is completed.
is sent to clear the contents of the register (1d) and reset the flip-flop (le).

That is, in the above configuration, the input data is held in the register (1d), and this is continued until the instruction that uses this data is executed, that is, until this unit is accessed, and the CPU (2) reads the data. It then releases the hold and prepares for the next input data.

The above embodiment will be explained in detail based on the timing chart of FIG.

The external device (
(not shown).

When input data DATEO to DATE7 exist and the strobe signal 5TRB becomes valid at timing B, the input DATEONDATE7 is input to the register (1d).
and its output Q. -Q7 is enabled and held according to input data.

Next, at scan timing A, when the instruction to read the main input data is executed and this unit is accessed, this is identified by the decoder (IC) and the gate signal G
The outputs q0 to Q7 of the register (1d) are output as data DBO to DB7 to the input/output data bus (3) via the output gate (1b) and read by CPtJ (2). Further, at timing C after this data output operation is completed, the decoder (Ic) generates a refractive signal CLS to clear the contents of the register (ld) and reset the flip-flop (le).

Here, the flip 70 knob (1e) is set by the strobe signal 5TRB to remember that input data has been read. This flip-flop (le) operates at the timing C after the output Qo""Q7 of the register (ld) is output to the input/output data bus (3) as described above.
It is reset by the clear signal CLS. In other words, the output signal BUSY of the flip-flop (1e) is valid from the time data is input until the CPU (2) reads it.
that the data has been read into the register (ld) and that the CP
t1 (2) is a flag indicating that the data has not been read. This BUSY signal is used in an external device (not shown), and if this Bt]SY signal is valid, it controls not to output the next data and prevents data from being read into the register (1d) in duplicate. It can be used to prevent.

〔Effect of the invention〕

As described above, according to the present invention, data can be held in a register from the time the data is input until the execution of an instruction that requires the data, so that the data duration Td is longer than the scan time Ts. Short but reliable CPU
This eliminates the drawback of conventional methods of calculating with incorrect data. In other words, there is no need to consider the relationship between Td and Ts, which has the advantage of increasing the degree of freedom in connecting the external device that outputs data and the programmable controller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data input unit explaining the data input method of the present invention, FIG. 2 is a signal waveform diagram of each part thereof, FIG. 3 is a block diagram of a conventional example corresponding to FIG. 1, and FIG.
FIG. 5 and FIG. 5 are waveform diagrams illustrating the relationship between data and scanning. In the figure, (1) is the data input crab unit, (2) is the CPU, (3) is the input/output data bus,
(°4) is the control line, (lb) is the output gate, (lc
) is a decoder, (ld) is a register, and (le) is a flip-flop. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A register that reads and holds input data consisting of a plurality of bits based on the input of a strobe signal, and clears the memory contents based on the input of a clear signal, and a register that is set based on the input of the strobe signal to enable the output signal. It is accessed through a flip-flop that stores the fact that the input data has been read and is reset based on the input of the clear signal to invalidate the output signal, and a control line that controls the input/output data bus based on the CPU program. a decoder that determines this when the data is output and sends out a gate signal, and also sends out the clear signal after the data output operation is completed; and an output that outputs the output of the register to the input/output data bus based on the input of the gate signal. The input data is held in the register by the strobe signal, and at the same time, the strobe signal is stored in the flip-flop and outputted to the outside, and when accessed by a program, the gate signal is output from the decoder. A data input method for a programmable controller characterized in that the output of a register is generated and outputted to an input/output data bus, and the register and flip-flop are reset by a decoder at a subsequent timing.