TWI587295B - Device for resetting hard disk drive - Google Patents

Description

Hard disk reset device

The present invention relates to a hard disk reset device, and more particularly to a hard disk reset device for a computer server system.

Today's global information explosion, so the form and capacity of information has also increased and increased, and the ever-increasing data waves have tested individuals, families and businesses. Therefore, the backup and safe preservation of data has become an important issue. In computer server systems, the most common storage device is a hard disk. In response to the huge amount of data, computer server systems have also evolved from a single hard drive architecture to a complex system with multiple hard drives. When the hard disk operation is different, in order to maintain the normal operation of the computer server system, it is usually necessary to reset the abnormally shaped hard disk by powering off or plugging and unplugging.

However, in practice, due to the increasingly complex and large size of the hard disk system, the traditional reset method is no longer sufficient. Therefore, how to reset the hard disk that is not working properly to improve the stability of the computer server system and reduce the probability of damage to the computer server system is one of the problems that developers should solve.

The present invention provides a hard disk reset device for resetting a hard disk that is not functioning properly, thereby improving the stability of the computer server system.

The hard disk reset device disclosed in the present invention comprises a decoder and a plurality of hard disk power modules. The decoder is electrically connected to the hard disk control module. The decoder includes a Serial General Purpose Input/Output (SGPIO) port and a plurality of output pins. Wherein, the serial input/output port receives the first serial input and output signal transmitted by the hard disk control module, and the first serial input The input signal includes a control command. The decoder selects a plurality of output pins according to the control command to output at least one reset signal. Each of the plurality of hard disk power modules is electrically connected to the corresponding output pin. Each hard disk power module is configured to provide at least one output power to supply power to a hard disk, and reset the at least one output power according to the reset signal.

In an embodiment of the invention, the decoder generates a parallel data according to the first serial input/output signal for decoding processing. The parallel data respectively corresponds to a plurality of output pins, and the decoder selects a plurality of output pins from the parallel data according to the control command to output at least one reset signal.

In an embodiment of the invention, the control command includes a plurality of symbols. The decoder reads a plurality of symbols to produce parallel data. The parallel data includes a plurality of bits, and the plurality of bits are in one-to-one correspondence with the plurality of symbols.

In an embodiment of the invention, the serial input/output port receives the second serial input and output signal and the third serial input and output signal. The second serial input/output signal defines a read period, and the third serial input/output signal defines a clock. The decoder reads a plurality of symbols of the control command according to the clock during reading.

In an embodiment of the invention, each hard disk power module in the hard disk power module includes a first power control unit and a first reset unit. The first power control unit includes a first enable control terminal, and the first power control unit controls the opening and closing of a first output power in the output power according to the voltage of the first enable control terminal. The first reset unit includes a first reset end, and the first reset end is electrically connected to the corresponding output pin for receiving the reset signal. The first reset unit is electrically connected to the first enable control terminal to control the voltage of the first enable control terminal according to the reset signal.

In an embodiment of the invention, the first reset unit further includes a first detecting end. The first reset unit controls the voltage of the first enable control terminal according to the voltage of the first detection terminal and the reset signal.

In an embodiment of the invention, the first reset unit includes a first transistor, a first resistor, and a second resistor. The gate of the first transistor is electrically connected to the first reset end through the first resistor, and the first reset end is electrically connected to the ground through the second resistor. The source of the first transistor is electrically connected to the ground, and the drain of the first transistor is electrically connected to the first enable control terminal. Reset signal will be the first reset terminal The voltage is raised from the low voltage level to the high voltage level, and the reset signal restores the voltage of the first reset terminal to a low voltage level after a predetermined time. When the voltage of the first reset terminal is at a low voltage level, the first transistor is not turned on. When the voltage of the first reset terminal is at a high voltage level, the first transistor is turned on, so that the first enable control terminal is conducted to the ground through the drain of the first transistor.

In an embodiment of the invention, the first reset unit further includes a second transistor, a third resistor, a first capacitor, and a first voltage terminal. The gate of the second transistor is electrically connected to the first detecting end, the source of the second transistor is electrically connected to the ground, and the drain of the second transistor is electrically connected to the first enabling control terminal. One end of the third resistor is electrically connected to the first voltage end, and the other end of the third resistor is electrically connected to the gate of the second transistor. One end of the first capacitor is electrically connected to the gate of the second transistor, and the other end of the first capacitor is grounded. When the voltage of the first detecting terminal is at a low voltage level, the second transistor is not turned on. When the voltage of the first detecting terminal is at a high voltage level, the second transistor is turned on, so that the first enabling control terminal is conducted to the ground through the drain of the second transistor.

In an embodiment of the invention, the first power control unit includes a current limiting switching element, a second voltage terminal, and a fourth resistor. The current limiting switching component includes a power input terminal, a ground terminal, a power output pin, and a first enabling control terminal. The power input end is electrically connected to the second voltage end, one end of the fourth resistor is electrically connected to the second voltage end, and the other end of the fourth resistor is electrically connected to the first enable control end. When the first enable control terminal is not turned to ground, the current limiting switch component outputs the first output power through the power output pin. When the first enable control terminal is turned to ground, the current limiting switch element stops outputting the first output power through the power output pin.

In an embodiment of the invention, the first power control unit further includes a second capacitor, one end of the second capacitor is electrically connected to the second voltage end, and the other end of the second capacitor is electrically connected to the ground.

In an embodiment of the invention, the first power control unit further includes a fifth resistor, and the current limiting switch component further includes a current limiting adjustment terminal. One end of the fifth resistor is electrically connected to the current limiting adjustment end, and the other end of the fifth resistor is electrically connected to the ground.

In an embodiment of the invention, each of the hard disk power modules further includes a second power control unit and a second reset unit. Wherein the second power control unit includes The second power control unit controls the opening and closing of the second output power in the output power according to the voltage of the second enable control terminal. The second reset unit includes a second reset end electrically connected to the first reset end for receiving the reset signal. The second reset unit is electrically connected to the second enable control terminal to control the voltage of the second enable control terminal according to the reset signal.

According to the hard disk reset device disclosed in the present invention, the hard disk reset device receives the serial input and output signals from the hard disk control module to reset the hard disk that is not functioning properly, thereby not only improving the computer server. The stability of the system also reduces the chance of damage to the computer server system. Therefore, in the increasingly complex and huge situation of the hard disk system, the cost and risk of system maintenance can be effectively reduced.

The above description of the present invention and the following description of the embodiments are intended to illustrate and explain the principles of the invention, and to provide a further explanation of the scope of the invention.

1‧‧‧ Hard disk reset device

10‧‧‧Decoder

12, 32, 42, 52‧‧‧ Hard disk power modules

100‧‧‧Serial input and output ports

102‧‧‧Output pin

S ₂₁ , S ₂₂ , S ₂₃ ‧‧‧ Serial input and output signals

t ₁ , t ₂ ‧‧ ‧ time point

320, 420, 520, 524‧ ‧ reset unit

322, 422, 522, 526‧‧‧ power control unit

3200, 4200, 5200, 5240‧‧‧ reset end

3202, 4202, 5242‧‧‧Detection

3220, 4220, 5260‧‧‧Enable control terminal

4222‧‧‧Power input power supply

4224‧‧‧ Grounding terminal

4226‧‧‧Power output pin

4228‧‧‧ Current limiting adjustment

Q ₁ , Q ₂ ‧‧‧O crystal

R ₁ , R ₂ , R ₃ , R ₄ , R ₅ ‧‧‧ resistance

C ₁ , C ₂ ‧‧‧ capacitor

V ₁ , V ₂ ‧‧‧ voltage end

SW ₁ ‧‧‧ current limiting switch components

FIG. 1 is a block diagram of a hard disk reset device according to an embodiment of the present invention.

FIG. 2 is a timing diagram of decoding according to an embodiment of the present invention.

FIG. 3 is a structural diagram of a hard disk power supply module according to an embodiment of the present invention.

FIG. 4 is a schematic circuit diagram of a hard disk power supply module according to an embodiment of the invention.

FIG. 5 is a structural diagram of a hard disk power supply module according to another embodiment of the present invention.

Please refer to FIG. 1 , which is a structural diagram of a hard disk reset device according to an embodiment of the present invention. The hard disk reset device is used in a computer server system. As shown in FIG. 1, the hard disk reset device 1 includes a decoder 10 and a plurality of hard disk power modules 12. The decoder 10 is electrically connected to the hard disk control module in the computer server system. For example, the hard disk control module can be a hard disk control module in a platform controller hub (PCH) or a south bridge chip, or a hard disk control module in a microprocessor. The decoder 10 further includes a Serial General Purpose Input/Output (SGPIO) port 100 and a plurality of output pins 102. Among them, serial input and output The port 100 is used for transmitting the first serial input and output signals of the hard disk control module, and the first serial input and output signals include control commands. The decoder 10 selects a plurality of output pins according to the control command to output at least one reset signal. Each of the plurality of hard disk power modules 12 is electrically connected to the corresponding output pin 102. Each of the hard disk power modules 12 is configured to provide at least one output power to supply power to a hard disk, and reset the at least one output power according to the reset signal. In practice, the decoder 10 can be a Complex Programmable Logic Device (CPLD), a Field Programmable Gate Array (FPGA), or other suitable programmable logic component, but this embodiment Not limited to this.

In an embodiment, the decoder 10 generates parallel data according to the first serial input/output signal, and the parallel data respectively corresponds to a plurality of output pins 102. The decoder 10 selects multiple outputs from the parallel data according to the control instruction. One of the pins 102 outputs a reset signal. For example, the parallel data may include 5 parallel bits, that is, the value of each parallel bit may be 0 or 1. Each parallel bit corresponds to one of a plurality of output pins 102. For example, when 5 parallel bits are 0, 0, 1, 0, and 0, respectively, the third output pin 102 is selected to output a reset signal. If the five parallel bits are 1, 0, 1, 0, and 0, respectively, the first and third output pins 102 are selected to output a reset signal. Thereby, the reset of the five hard disks can be controlled by using the first serial input/output signal.

In another example, multiple parallel bits may correspond to a value. The decoder 10 can select a plurality of output pins 102 according to the value and simultaneously output a reset signal by respectively different values corresponding to one of the plurality of output pins 102 or a plurality of output pins 102. For example, three parallel bits correspond to a value, and the following table defines the correspondence between the value and the output pin 102.

Thereby, the serial input/output signal can be used to control the reset of 3 hard disks. In practice, the correspondence between the value and the output pin 102 is not limited thereto, and those skilled in the art to which the invention pertains may design different correspondences according to actual needs.

Please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a timing diagram of a serial input/output signal according to an embodiment of the present invention. The horizontal axis is the time axis. For example, the first serial input/output signal S ₂₃ can be a serial input/output data output (SGPIO_DOUT) signal, which includes a control instruction, and the control instruction includes a plurality of symbols, each symbol Can be a high level symbol or a low level symbol. The decoder 10 reads a plurality of symbols to generate parallel data, the parallel data includes a plurality of bits, and the plurality of bits are in one-to-one correspondence with the plurality of symbol systems. For example, as shown in FIG. 2, the first three symbols of the control instruction are a low level symbol, a high level symbol, and a high level symbol. Therefore, the first three bits of the generated parallel data can be 0, 1, and 1, respectively. In practice, the second serial input/output signal S ₂₁ and the third serial input/output signal S ₂₂ can be received by the serial input/output port 100. For example, the second serial input/output signal S ₂₁ can be a serial input/output load (SGPIO_LOAD) signal for defining a read period (time point t ₁ to time point t ₂ ). The third serial input/output signal S ₂₂ can be a serial input/output clock (SGPIO_CLK) signal for defining the clock. Thereby, the decoder 10 can periodically read the symbols in the control instructions according to the clock during reading to generate parallel data.

Please refer to FIG. 3, which is a structural diagram of a hard disk power supply module according to an embodiment of the present invention. The hard disk power module 32 includes a first reset unit 320 and a first power control unit 322. The first power control unit 322 includes a first enable control terminal 3220. The first power control unit 322 controls the opening and closing of the first output power in the output power according to the voltage of the first enable control terminal 3220. Furthermore, the first reset unit 320 includes a first reset terminal 3200. The first reset terminal 3200 is electrically connected to the corresponding output pin 102 of the decoder 10 in FIG. 1 for receiving the reset signal. In addition, the first reset unit 320 is electrically connected to the first enable control terminal 3220 to control the voltage of the first enable control terminal 3220 according to the reset signal.

Please continue to refer to Figure 3. In an embodiment, the first reset unit 320 further includes a first detecting end 3202. In practice, the first detecting end 3202 is used to electrically connect to a hard disk to connect There is a signal on the hard disk. In this way, whether the hard disk power module 32 is connected to the hard disk can be confirmed by the hard disk presence signal. The first reset unit 320 can control the voltage of the first enable control terminal 3220 according to the voltage of the first detection terminal 3202 and the reset signal received by the first enable control terminal 3220. For example, when the first reset unit 320 does not receive the reset signal, and the hard disk presence signal confirms that the hard disk power module 32 is not connected to the hard disk, the first reset unit 320 controls the first The voltage of the control terminal 3220 is enabled to turn off the first output power. In this way, unnecessary power supply can be avoided to improve system efficiency.

Please refer to FIG. 4 , which is a circuit diagram of a hard disk power module according to an embodiment of the invention. The first reset unit 420 includes a first transistor Q ₁ , a first resistor R _{1 ,} and a second resistor R ₂ . The gate of the first transistor Q ₁ is electrically connected to the first reset terminal 4200 through the first resistor R ₁ , and the first reset terminal 4200 is electrically connected to the ground through the second resistor R ₂ . Furthermore, the source of the first transistor Q ₁ is electrically connected to the ground, and the drain of the first transistor Q ₁ is electrically connected to the first enable control terminal 4220. For example, when a reset is required, the reset signal raises the voltage of the first reset terminal 4200 from the low voltage level to the high voltage level, and the reset signal will be the first reset end after a preset time. The voltage of the 4200 returns to the low voltage level. When the voltage of the first reset terminal 4200 is at a low voltage level, the first transistor Q ₁ is not turned on. When the voltage of the first reset terminal 4200 is at a high voltage level, the first transistor Q ₁ turns on, and an enable control terminal of the first electrode 4220 is conducted to the ground through the drain of the first transistor Q ₁ '. Thereby, the voltage of the first enable control terminal 4220 can be controlled according to the reset signal.

Referring to FIG. 4 , in another embodiment, the first reset unit 420 further includes a second transistor Q ₂ , a third resistor R ₃ , a first capacitor C _{1 ,} and a first voltage terminal V ₁ . The gate of the second transistor Q ₂ is electrically connected to the first detecting end 4202 , the source of the second transistor Q ₂ is electrically connected to the ground, and the drain of the second transistor Q ₂ is electrically connected to the first The control terminal 4220 is enabled. Furthermore, one end of the third resistor R ₃ is electrically connected to the first voltage terminal V ₁ , and the other end of the third resistor R ₃ is electrically connected to the gate of the second transistor Q ₂ . Further, one end of the first capacitor C ₁ is electrically connected to the gate of the second transistor Q ₂ , and the other end of the first capacitor C ₁ is grounded. For example, when the hard disk has a signal indicating connection with the hard disk, the voltage of the first detecting terminal 4202 is at a low voltage level, and the second transistor Q _{2 is} not turned on. When the hard disk presence signal indicates that the hard disk is not connected to the hard disk, when the voltage of the first detecting terminal 4202 is at the high voltage level, the second transistor Q _{2 is} turned on, so that the first enabling control terminal 4220 transmits the second transistor Q. The bungee of ₂ is turned to the ground. Thereby, the voltage of the first enable control terminal 4220 can be controlled according to the reset signal and the hard disk presence signal.

Referring to FIG. 4, in still another embodiment, the first power control unit 422 includes a current limiting switching element SW ₁ , a second voltage terminal V _{2 ,} and a fourth resistor R ₄ . The current limiting switch element SW ₁ includes a power input terminal 4222, a ground terminal 4224, a power output pin 4226, and a first enable control terminal 4220. The power input terminal 4222 is electrically connected to the second voltage terminal V ₂ , and one end of the fourth resistor R ₄ is electrically connected to the second voltage terminal V ₂ , and the other end of the fourth resistor is electrically connected to the first enable control terminal 4220 . For example, when the first enable control terminal 4220 is not conducting to ground, the current limiting switch element SW ₁ through the power supply output pin 4226 outputs the first power supply output. The first output power source is supplied by the second voltage terminal V ₂ . When the first enabling control terminal 4220 is turned to the ground, the current limiting switching element SW ₁ stops outputting the first output power through the power output pin 4226.

In practice, the first power control unit 422 may further include a second capacitor C ₂ . One end of the second capacitor C ₂ is electrically connected to the second voltage terminal V ₂ , and the other end of the second capacitor C ₂ is electrically connected to the ground for filtering. In addition, the first power control unit 422 may further include a fifth resistor R ₅ , and the current limiting switch element SW ₁ further includes a current limiting adjustment terminal 4228 . The one end of the fifth resistor R ₅ is electrically connected to the current limiting adjustment end 4228 , and the other end of the fifth resistor R ₅ is electrically connected to the ground. Thus, by adjusting the resistance value of the fifth resistor R _5, the size of the first control current output of the power supply.

Please refer to Figure 1 and Figure 4 together to illustrate how the serial input and output signals can be used to control the operation of the hard disk power reset. First, when all hard disks are operating normally, the first reset terminal 4200 is at a low voltage level. Therefore, the first transistor Q _{1 is} not turned on. At this time, if the hard disk has a signal indicating that the connection with the hard disk is correct, the voltage of the first detecting end 4202 is at a low voltage level, so that the second transistor Q _{2 is} also not turned on. Thus, the first enabling control voltage terminal 4220 is at a high voltage level, so that the first output 4226 the output of the power limiting switch element SW ₁ through the power supply output pin.

However, when the hard disk control module detects that the hard disk is in an abnormal state, the hard disk control module notifies the hard disk reset device 1 by using the serial input and output signals. When the hard disk reset device 1 receives the serial input and output signals, it is convenient to decode with the decoder 10 to determine which hard disk to reset. Once determined, the decoder 10 generates a pulse signal as a reset signal and transmits it to the corresponding hard disk power module 12. The pulse signal boosts the voltage of the first reset terminal 4200 from the low voltage level to the high voltage level to turn on the first transistor Q ₁ , so that the first enable control terminal 4220 transmits the first transistor Q ₁ . The bungee is turned to the ground. When the first enabling control terminal 4220 to be turned on, the current limiting switch element SW ₁ will stop the power supply output through a first output pin 4226 output power. After the end of the pulse signal, the voltage of the first reset terminal 4200 will resume from the low voltage level to a low voltage level, so that the current limiting switch element SW ₁ through the power recovery output pin 4226 outputs the first power supply output. This completes the process of a hard disk power reset.

Please refer to FIG. 5 , which is a structural diagram of a hard disk power module according to another embodiment of the present invention. In practice, a hard disk can be driven by two different voltage sources, such as a 5 volt power supply and a 12 volt power supply. Therefore, when performing the hard disk power reset procedure, both power supplies must be reset. Therefore, the hard disk power module 52 includes the first reset unit 520 and the first power control unit 522. The coupling relationship and operation principle are the same as those in the embodiment shown in FIG. 3, and details are not described herein again. Different from FIG. 3 , the hard disk power module 52 further includes a second reset unit 524 and a second power control unit 526 . The second power control unit 526 includes a second enable control terminal 5260. The second power control unit 526 controls the opening and closing of the second output power in the output power according to the voltage of the second enable control terminal 5260. Furthermore, the second reset unit 524 includes a second reset terminal 5240. The second reset end 5240 is electrically connected to the first reset end 5200 for receiving the reset signal. In addition, the second reset unit 524 is electrically connected to the second enable control terminal 5260 to control the voltage of the second enable control terminal 5260 according to the reset signal.

In addition, the second reset unit 524 may further include a second detecting end 5242 to receive a hard disk presence signal. The second detecting end 5242 controls the voltage of the second enabling control terminal 5260 according to the voltage of the second detecting end 5242 and the reset signal. In a practical manner, the circuit configuration related to the second reset unit 524 and the second power control unit 526 and the operation mode thereof are similar to the first reset unit 520 and the first power control unit 522, and details are not described herein again. .

In summary, the hard disk reset device receives serial input and output from the hard disk control module. The signal is used to reset the hard disk that is not working properly, which not only improves the stability of the computer server system, but also reduces the chance of damage to the computer server system. In addition, with the decoder with programming flexibility, the required reset mechanism can be designed according to the characteristics of the computer server system, for example, converting the serial input signal into parallel data, thereby improving the efficiency of the reset program. Therefore, in the increasingly complex and huge situation of the hard disk system, the cost and risk of system maintenance can be effectively reduced.

Although the embodiments of the present invention are disclosed above, it is not intended to limit the present invention, and those skilled in the art, regardless of the spirit and scope of the present invention, the shapes, configurations, and features described in the scope of the present application. And the number of modifications may be made, and the scope of patent protection of the present invention shall be determined by the scope of the patent application attached to the specification.

1‧‧‧ Hard disk reset device

10‧‧‧Decoder

12‧‧‧ Hard disk power module

100‧‧‧ input

102‧‧‧Output pin

Claims (12)

A hard disk reset device for a computer server system, comprising: a decoder electrically connected to a hard disk control module, the decoder comprising: a serial general purpose input/output (SGPIO) a port for transmitting a control command of the hard disk control module; and a plurality of output pins; wherein the serial input/output port transmits a first serial input/output signal, the first serial input and output signal Including the control command, the decoder selects the plurality of output pins according to the control command to output at least one reset signal; and a plurality of hard disk power modules, wherein each of the hard disk power modules is electrically connected The output pin, each of the hard disk power modules provides an output power supply to a hard disk, and resets the output power according to the reset signal. The hard disk reset device of claim 1, wherein the decoder generates a parallel data according to the first serial input/output signal, and the parallel data respectively corresponds to a plurality of output pins, and the decoding The plurality of output pins are selected from the parallel data according to the control command to output the at least one reset signal. The hard disk reset device of claim 2, wherein the control command comprises a plurality of symbols, the decoder reads the plurality of symbols to generate the parallel data, the parallel data comprising a plurality of bits, the plurality of bits The bit corresponds to the plurality of symbols one by one. The hard disk reset device of claim 3, wherein the serial input/output port receives a second serial input/output signal and a third serial input/output signal, and the second serial input/output signal defines a read During the fetching period, the third serial input/output signal defines a clock, and the decoder reads the plurality of symbols of the control instruction according to the clock during the reading. The hard disk reset device of claim 1, wherein each of the hard disk power modules The power module includes: a first power control unit, including a first enable control terminal, wherein the first power control unit controls the opening of a first output power of the output power according to the voltage of the first enable control terminal And a first resetting unit, the first resetting end is electrically connected to the corresponding output pin for receiving the reset signal, and the first resetting unit is electrically The first enabling control terminal is connected to control the voltage of the first enabling control terminal according to the reset signal. The hard disk reset device of claim 5, wherein the first reset unit further includes a first detecting end, and the first reset unit controls the voltage according to the voltage of the first detecting end and the reset signal The first consistent control terminal voltage. The hard disk reset device of claim 6, wherein the first reset unit comprises a first transistor, a first resistor, and a second resistor, wherein the gate of the first transistor passes through the first The resistor is electrically connected to the first reset end, the first reset end is electrically connected to the ground through the second resistor, and the source of the first transistor is electrically connected to the ground, the drain of the first transistor Electrically connecting the first enabling control terminal, the reset signal boosting the voltage of the first reset terminal from a low voltage level to a high voltage level, and the reset signal is to be used after a preset time The voltage of the first reset terminal is restored to the low voltage level, and when the voltage of the first reset terminal is at the low voltage level, the first transistor is not turned on, and when the voltage of the first reset terminal is at the high voltage When the level is in position, the first transistor is turned on, so that the first enable control terminal is conducted to the ground through the drain of the first transistor. The hard disk reset device of claim 7, wherein the first reset unit further includes a second transistor, a third resistor, a first capacitor, and a first voltage terminal, wherein the second transistor The gate is electrically connected to the first detecting end, the source of the second transistor is electrically connected to the ground, and the drain of the second transistor is electrically connected to the first enabling control terminal, the third resistor One end of the first resistor is electrically connected to the first voltage end, and the other end of the third resistor is electrically connected to the gate of the second transistor, and one end of the first capacitor is electrically connected to the gate of the second transistor. The other end of a capacitor is grounded. When the voltage of the first detecting terminal is at the low voltage level, the second transistor is not turned on when the first detecting When the voltage of the measuring terminal is at the high voltage level, the second transistor is turned on, so that the first enabling control terminal is conducted to the ground through the drain of the second transistor. The hard disk reset device of claim 5, wherein the first power control unit comprises a current limiting switch component, a second voltage terminal, and a fourth resistor, the current limiting switch component comprising a power input terminal, a grounding end, a power output pin, and the first enabling end, wherein the power input is electrically connected to the second voltage end, and one end of the fourth resistor is electrically connected to the second voltage end, the fourth resistor The other end is electrically connected to the first enabling control terminal, and when the first enabling control terminal is not conducting to the ground, the current limiting switching component outputs the first output power through the power output pin, when the first The control terminal is turned to the ground, and the current limiting switch element stops outputting the first output power through the power output pin. The hard disk reset device of claim 9, wherein the first power control unit further includes a second capacitor, one end of the second capacitor is electrically connected to the second voltage end, and the other end of the second capacitor is electrically Sexual connection to the ground. The hard disk reset device of claim 9, wherein the first power control unit further includes a fifth resistor, the current limiting switch component further includes a current limiting adjustment end, and one end of the fifth resistor is electrically connected to the The current limiting adjustment end, the other end of the fifth resistor is electrically connected to the ground. The hard disk reset device of claim 5, wherein each of the hard disk power modules further includes: a second power control unit, including a second enable control terminal, The second power control unit controls the opening and closing of a second output power of the output power according to the voltage of the second enable control terminal; and a second reset unit, including a second reset end, the second The reset end is electrically connected to the first reset end for receiving the reset signal, and the second reset unit is electrically connected to the second enable control end to control the second enable according to the reset signal The voltage at the control terminal.